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Visitor
Visitor
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Registered: ‎11-03-2020

CCLK does not toggle in SPI Master Mode

Hello,

 

i have set up a custom board with an XC7S50 FPGA working in QSPI Master Mode with a connected Flash Memory and an Microprocessor monitoring the programming lines and toggling PROGRAM_B.

When the Processor pulls PROGRAM_B low, INIT_B falls and rises after PROGRAM_B rises again, all according to the datasheet. But after Chip Select (FCS_B) falls, CCLK does not start. DONE remains low since the programming sequence never completes. I've already checked the voltage supply and mode pins, EMCCLK is floating. Is there any other possible cause i could look for?

When connected to VIVADO using an Platform Cable, the connected Flash Memory cannot be detected either. Directly programming the FPGA via JTAG works fine.

I've attached some screens showing the connections used for configuration and the memory. Since this is a prototype the mode pins are connected to jumpers, the clk can be switched to the microprocessor as an alternate programming source. I've checked the signals directly at the FPGA to ensure it is not a problem of the connections.

fpga_modes_config.PNGfpga_prog_config.PNGfpga_qspi_config.PNG

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Moderator
Moderator
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Registered: ‎06-05-2013

Maybe I am missing something here. Your first screenshot mentions master SPI mode pins as 011 which is wrong. It should be 001. (M2:0) Refer to page#21 of UG470 https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Don’t forget to reply, kudo, and accept as solution.
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Visitor
Visitor
250 Views
Registered: ‎11-03-2020

You are right, it's wrong in the picture. I've already corrected this, sorry.

 

Also, even with the wrong mode code it should still be possible to access the flash memory with vivado, is this correct? The flash is not accessible from vivado, it can't read the flash properties, and the cclk does not toggle in this scenario, too.

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Moderator
Moderator
238 Views
Registered: ‎06-05-2013

You are using a supported flash. Can you share the Vivado log instead?

Open Vivado HW manager --> Connect to JTAG chain --> Add your flash device to Vivado --> Try to perform erase or blank check operation. Share the log.
Does it show ID as all 00 or unable to read the device property?
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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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Visitor
Visitor
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Registered: ‎11-03-2020

This is the log from performing an Erase and Blank Check. Apparently it is unable to read the device properties. The flash setup is mostly taken from the CMOD S7 Reference Design for XC7S25 (with adjusted pin configurations), i hoped that this way i would avoid exactly such a problem.

 

set_property PROGRAM.ADDRESS_RANGE {entire_device} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.FILES [list "F:/FPGC/flash.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.PRM_FILE {F:/FPGC/MMI_FPGA_VHDL_MOD.runs/impl_1/flash.prm} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.BLANK_CHECK 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CFG_PROGRAM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.VERIFY 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
startgroup
create_hw_bitstream -hw_device [lindex [get_hw_devices xc7s50_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7s50_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7s50_0] 0]; refresh_hw_device [lindex [get_hw_devices xc7s50_0] 0];
INFO: [Labtools 27-3164] End of startup status: HIGH
INFO: [Labtools 27-2302] Device xc7s50 (JTAG device index = 0) is programmed with a design that has 1 SPI core(s).
WARNING: [Labtools 27-3413] Dropping logic core with cellname:'u_ila_0' at location 'uuid_23E7D65A79BC59F7BC47406C1714DFAE' from probes file, since it cannot be found on the programmed device.
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7s50_0] 0]]
Mfg ID : 0 Memory Type : 0 Memory Capacity : 0 Device ID 1 : 0 Device ID 2 : 0
CRITICAL WARNING: [Labtools 27-2251] Unable to read device properties. Please make sure that the proper configuration memory part is selected.

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