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sutej
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Registered: ‎07-06-2017

CFGBVS connected to 1.8V and Bank 0 , 14, 15 powered with 1.8V

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Hello,

 

We are using Artix-7 100t device.

We have made a mistake in the schematic, We have connected 1.8V on CFGBVS pin instead of GND.

 

Our boot configuration device is 1.8V and Bank 0, 14, 15 are powered with 1.8V.

 

Will this be a problem ? I know as per datasheet we should not left the CFGBVS pin floating but can we cut the trace and keep it open to see the functionality ?

 

--Anil SUtej 

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gnarahar
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Registered: ‎07-23-2015

 

 Will this be a problem ? I know as per datasheet we should not left the CFGBVS pin floating but can we cut the trace and keep it open to see the functionality ?


We cannot predict since this is unknown territory and we do not characterize such scenario. 

- Giri
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gnarahar
Moderator
Moderator
4,481 Views
Registered: ‎07-23-2015

 

 Will this be a problem ? I know as per datasheet we should not left the CFGBVS pin floating but can we cut the trace and keep it open to see the functionality ?


We cannot predict since this is unknown territory and we do not characterize such scenario. 

- Giri
------------------------------------------------------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
If starting with Versal take a look at our Versal Design Process Hub and our Versal Blogs
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View solution in original post

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sutej
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Registered: ‎07-06-2017

 Hello Gnarahar,

 

Thank you for the reply.

I will risk a board and check the functionality.

 

--Anil 

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ralfk
Xilinx Employee
Xilinx Employee
2,526 Views
Registered: ‎10-11-2007

Please fix the issue. Floating the pin is not a fix because you don't know what voltage the CFGBVS pin will see. You are not likely to see damage to the IOs. But they are configured for 3.3V and Vin = 1.8V may not be enough to meet that threshold. It's close, but I wouldn't rely on that consistently working even if it does in the Lab. 

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