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wuyouniyanhu
Adventurer
Adventurer
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Registered: ‎03-28-2020

CPU_RESET & Reset_After_Config

wuyouniyanhu_0-1631501729857.pngwuyouniyanhu_1-1631501753350.png

On the VCU128 board we are using, according to the manual and schematic diagram, you can see that there is a reset button (BM29) for resetting FPGA on the board.

There is a bit of confusion about the reset problem of FPGA: Whenever we use VIVADO to download a bitstream file to the device, even if no one presses the button to reset manually after downloading, the logic inside the FPGA always seems to be able to run normally. So, is there an automatic reset mechanism that will be automatically triggered once when the bit rate is downloaded? What is the mechanism of this automatic reset? How is it implemented by hardware circuits inside the FPGA? Can it completely replace the effect of manually pressing the button?

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iguo
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

Yes there is a global automatica FPGA reset at the end of configuration. It's called GSR and FPGA has dedicated network to run it.

I don't track this CPU_RESET signal on VCU128; it seems a custom reset implemented by GPIO. You can design your own maual reset as well. GSR will always work but you can implement your own reset according to the system requirements.

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