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Scholar
Scholar
369 Views
Registered: ‎04-27-2010

Can start Artix config sequence

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I have an Artix design that has a Micron SPI memory attached to the config pins. There is also a MCU that is connected to the FPGA using a parallel bus. I can program the flash memory using this parallel bus (via a SPI controller in the design). I have done this and read back the bitstream and confirmed that it is correct. The bitstream uses compression for ref. I am now trying to configure the FPGA using the MCU as I have the PROG_B, INIT and DONE pins connected to the MCU. I initially set PROG_B low for about 100us. The INIT goes low then back to high. But the DONE pin never goes high.Is there something else I should be doing? Thanks  

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Scholar
Scholar
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Registered: ‎04-27-2010

Thanks for the suggestions. It seems that the issue was with the JTAG attached.

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Registered: ‎01-22-2015

Some things to check:

  1. Are M[2:0]=001 (Master SPI)
  2. Has MCU released control of flash data and clock lines so that FPGA can control these lines?
  3. Use oscope to check for clean logic on data and clock lines with flash.
  4. Is pullup resistor installed on DONE line?
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324 Views
Registered: ‎06-21-2017

Excellent suggestions.  Once you have done these, use the oscope to look at the data for the header in the bit stream.  Make sure it isn't byte swapped.  This is pretty easy to do when going from one processor to another.  I don't remember the header off the top of my head, but it is in the Configuration User's Guide.

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Xilinx Employee
Xilinx Employee
217 Views
Registered: ‎03-07-2018

Hi @beandigital 

You can refer to XAPP583 (v1.0) with its reference design and  XAPP1188 (v1.1) with its reference design to check your setup and design setting.  

Regards,
Bhushan

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Scholar
Scholar
211 Views
Registered: ‎04-27-2010

Thanks for the suggestions. It seems that the issue was with the JTAG attached.

View solution in original post

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