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os177
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1,232 Views
Registered: ‎05-22-2020

Can't change TYPE of RTL-module pin

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Vivado tells me, that two pins I connected are not of the same type (one is a clock directly from my ZYNQS and one is a RTL-module pin (undefined)). When I want to change this by "set_property TYPE clk [get_bd_pins led_0/clk_led]" I get the following error: "ERROR: [Common 17-107] Cannot change read-only property 'TYPE'." I know, how to deal with this, if it was a 'normal' IP core, however led_0 is a module (written in verilog) of my own... How can I change the read-only property?! ('set_property IS_MANAGED {0} [get_ips led_0]' does of course not work, as led_0 is not an ip...)

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markgraf
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Adventurer
1,092 Views
Registered: ‎04-04-2018

Change the module port in your led verilog source from clk_led to led_clk and reconnect to FCLK_CLK0 in IPI

Change the module port in your squarewave module from clk_sq to sq_clk and reconnect to FCLK_CLK1 in IPI.

validate block design

export block design to overwrite .tcl script

you should now be able to generate bd without warning.

IPI wants to see clock signals named as such from UG1118

table 2-3:Clock Signal Naming [*_]clk [*_]clkin [*_]clock[_*] [*_]aclk [*_]aclkin

 

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

View solution in original post

12 Replies
1,224 Views
Registered: ‎07-23-2019

 

what is 'ZYNQS'? The Zynq PS?

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os177
Visitor
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Registered: ‎05-22-2020

Oh yeah, sorry - VERY bad type.. I mean, I am making a project including a Xilinx zynq-7000 processor (XC7Z010-1CLG400C)  

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vsrunga
Xilinx Employee
Xilinx Employee
1,206 Views
Registered: ‎07-11-2011

Hi, 

Can you please issue below command after opening the bd and share its output ?

write_bd_tcl my_bd.tcl

script named my_bd.tcl will be found in your pwd 

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os177
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Registered: ‎05-22-2020
Oh yeah, sorry - VERY bad type.. I mean, I am making a project including a Xilinx zynq-7000 processor (XC7Z010-1CLG400C)
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os177
Visitor
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1,200 Views
Registered: ‎05-22-2020
You mean this?
open_bd_design {/mnt/c/users/ingrid/documents/work/fpga/myproject/myproject.srcs/sources_1/bd/project_bd/project_bd.bd}
Adding cell -- xilinx.com:ip:processing_system7:5.5 - processing_system7_0
Adding cell -- localdomain:module_ref:squarewave:1.0 - squarewave_0
Adding cell -- localdomain:module_ref:led:1.0 - led_0
WARNING: [BD 41-1731] Type mismatch between connected pins: /processing_system7_0/FCLK_CLK0(clk) and /led_0/clk_led(undef)
WARNING: [BD 41-1731] Type mismatch between connected pins: /processing_system7_0/FCLK_CLK1(clk) and /squarewave_0/clk_sq(undef)
Successfully read diagram <project_bd> from BD file </mnt/c/users/ingrid/documents/work/fpga/myproject/myproject.srcs/sources_1/bd/project_bd/project_bd.bd>
write_bd_tcl project_bd.tcl
INFO: [BD 5-148] Tcl file written out </mnt/c/users/ingrid/documents/work/fpga/project_bd.tcl>.
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ashishd
Xilinx Employee
Xilinx Employee
1,197 Views
Registered: ‎02-14-2014

Hi @os177 ,

Yes, share this project_bd.tcl which got written here - /mnt/c/users/ingrid/documents/work/fpga/

Regards,
Ashish
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os177
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Registered: ‎05-22-2020

################################################################
# This is a generated script based on design: project_bd
#
# Though there are limitations about the generated script,
# the main purpose of this utility is to make learning
# IP Integrator Tcl commands easier.
################################################################

namespace eval _tcl {
proc get_script_folder {} {
set script_path [file normalize [info script]]
set script_folder [file dirname $script_path]
return $script_folder
}
}
variable script_folder
set script_folder [_tcl::get_script_folder]

################################################################
# Check if script is running in correct Vivado version.
################################################################
set scripts_vivado_version 2017.2
set current_vivado_version [version -short]

if { [string first $scripts_vivado_version $current_vivado_version] == -1 } {
puts ""
catch {common::send_msg_id "BD_TCL-109" "ERROR" "This script was generated using Vivado <$scripts_vivado_version> and is being run in <$current_vivado_version> of Vivado. Please run the script in Vivado <$scripts_vivado_version> then open the design in Vivado <$current_vivado_version>. Upgrade the design by running \"Tools => Report => Report IP Status...\", then run write_bd_tcl to create an updated script."}

return 1
}

################################################################
# START
################################################################

# To test this script, run the following commands from Vivado Tcl console:
# source project_bd_script.tcl


# The design that will be created by this Tcl script contains the following
# module references:
# led, squarewave

# Please add the sources of those modules before sourcing this Tcl script.

# If there is no project opened, this script will create a
# project, but make sure you do not have an existing project
# <./myproj/project_1.xpr> in the current working folder.

set list_projs [get_projects -quiet]
if { $list_projs eq "" } {
create_project project_1 myproj -part xc7z010clg400-1
}


# CHANGE DESIGN NAME HERE
set design_name project_bd

# If you do not already have an existing IP Integrator design open,
# you can create a design using the following command:
# create_bd_design $design_name

# Creating design if needed
set errMsg ""
set nRet 0

set cur_design [current_bd_design -quiet]
set list_cells [get_bd_cells -quiet]

if { ${design_name} eq "" } {
# USE CASES:
# 1) Design_name not set

set errMsg "Please set the variable <design_name> to a non-empty value."
set nRet 1

} elseif { ${cur_design} ne "" && ${list_cells} eq "" } {
# USE CASES:
# 2): Current design opened AND is empty AND names same.
# 3): Current design opened AND is empty AND names diff; design_name NOT in project.
# 4): Current design opened AND is empty AND names diff; design_name exists in project.

if { $cur_design ne $design_name } {
common::send_msg_id "BD_TCL-001" "INFO" "Changing value of <design_name> from <$design_name> to <$cur_design> since current design is empty."
set design_name [get_property NAME $cur_design]
}
common::send_msg_id "BD_TCL-002" "INFO" "Constructing design in IPI design <$cur_design>..."

} elseif { ${cur_design} ne "" && $list_cells ne "" && $cur_design eq $design_name } {
# USE CASES:
# 5) Current design opened AND has components AND same names.

set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 1
} elseif { [get_files -quiet ${design_name}.bd] ne "" } {
# USE CASES:
# 6) Current opened design, has components, but diff names, design_name exists in project.
# 7) No opened design, design_name exists in project.

set errMsg "Design <$design_name> already exists in your project, please set the variable <design_name> to another value."
set nRet 2

} else {
# USE CASES:
# No opened design, design_name not in project.
# 9) Current opened design, has components, but diff names, design_name not in project.

common::send_msg_id "BD_TCL-003" "INFO" "Currently there is no design <$design_name> in project, so creating one..."

create_bd_design $design_name

common::send_msg_id "BD_TCL-004" "INFO" "Making design <$design_name> as current_bd_design."
current_bd_design $design_name

}

common::send_msg_id "BD_TCL-005" "INFO" "Currently the variable <design_name> is equal to \"$design_name\"."

if { $nRet != 0 } {
catch {common::send_msg_id "BD_TCL-114" "ERROR" $errMsg}
return $nRet
}

##################################################################
# DESIGN PROCs
##################################################################



# Procedure to create entire design; Provide argument to make
# procedure reusable. If parentCell is "", will use root.
proc create_root_design { parentCell } {

variable script_folder

if { $parentCell eq "" } {
set parentCell [get_bd_cells /]
}

# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_msg_id "BD_TCL-100" "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}

# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_msg_id "BD_TCL-101" "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}

# Save current instance; Restore later
set oldCurInst [current_bd_instance .]

# Set parent object as current
current_bd_instance $parentObj


# Create interface ports
set DDR [ create_bd_intf_port -mode Master -vlnv xilinx.com:interface:ddrx_rtl:1.0 DDR ]
set FIXED_IO [ create_bd_intf_port -mode Master -vlnv xilinx.com:display_processing_system7:fixedio_rtl:1.0 FIXED_IO ]

# Create ports
set led_out [ create_bd_port -dir O -from 7 -to 0 led_out ]
set pwr_out [ create_bd_port -dir O -from 0 -to 0 pwr_out ]

# Create instance: led_0, and set properties
set block_name led
set block_cell_name led_0
if { [catch {set led_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $led_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}

# Create instance: processing_system7_0, and set properties
set processing_system7_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:processing_system7:5.5 processing_system7_0 ]
set_property -dict [ list \
CONFIG.PCW_EN_CLK1_PORT {1} \
CONFIG.PCW_EN_RST0_PORT {0} \
CONFIG.PCW_EN_RST1_PORT {1} \
CONFIG.PCW_USE_M_AXI_GP0 {0} \
] $processing_system7_0

# Create instance: squarewave_0, and set properties
set block_name squarewave
set block_cell_name squarewave_0
if { [catch {set squarewave_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_msg_id "BD_TCL-105" "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $squarewave_0 eq "" } {
catch {common::send_msg_id "BD_TCL-106" "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}

# Create interface connections
connect_bd_intf_net -intf_net processing_system7_0_DDR [get_bd_intf_ports DDR] [get_bd_intf_pins processing_system7_0/DDR]
connect_bd_intf_net -intf_net processing_system7_0_FIXED_IO [get_bd_intf_ports FIXED_IO] [get_bd_intf_pins processing_system7_0/FIXED_IO]

# Create port connections
connect_bd_net -net led_0_licht_raus [get_bd_ports led_out] [get_bd_pins led_0/licht_raus]
connect_bd_net -net processing_system7_0_FCLK_CLK0 [get_bd_pins led_0/clk_led] [get_bd_pins processing_system7_0/FCLK_CLK0]
connect_bd_net -net processing_system7_0_FCLK_CLK1 [get_bd_pins processing_system7_0/FCLK_CLK1] [get_bd_pins squarewave_0/clk_sq]
connect_bd_net -net processing_system7_0_FCLK_RESET1_N [get_bd_pins processing_system7_0/FCLK_RESET1_N] [get_bd_pins squarewave_0/rst_n]
connect_bd_net -net squarewave_0_sq_wave [get_bd_ports pwr_out] [get_bd_pins squarewave_0/sq_wave]

# Create address segments


# Restore current instance
current_bd_instance $oldCurInst

save_bd_design
}
# End of create_root_design()


##################################################################
# MAIN FLOW
##################################################################

create_root_design ""


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markgraf
Adventurer
Adventurer
1,185 Views
Registered: ‎04-04-2018

I am assuming you are instantiating your custom module into IPI based on your signal descriptions. I am not familiar with the commands you are trying to execute. You could try adding this signal interface directive to your verilog source:

// Declare the attributes above the port declaration
(* X_INTERFACE_INFO = "xilinx.com:signal:clock:1.0 clk_led CLK" *)

IPI will automatically infer signals if they are named in a certain way. if you change the name of the clock port in your verilog module to led_clk, it should work.

Lots of good information in UG1118:

https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug1118-vivado-creating-packaging-custom-ip.pdf

 

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com
os177
Visitor
Visitor
1,162 Views
Registered: ‎05-22-2020
Mhh.. Suggested command did not make a difference... Well,I am able to generate bitstreams etc., but it would be nice to have everything in place I guess.
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markgraf
Adventurer
Adventurer
1,093 Views
Registered: ‎04-04-2018

Change the module port in your led verilog source from clk_led to led_clk and reconnect to FCLK_CLK0 in IPI

Change the module port in your squarewave module from clk_sq to sq_clk and reconnect to FCLK_CLK1 in IPI.

validate block design

export block design to overwrite .tcl script

you should now be able to generate bd without warning.

IPI wants to see clock signals named as such from UG1118

table 2-3:Clock Signal Naming [*_]clk [*_]clkin [*_]clock[_*] [*_]aclk [*_]aclkin

 

Steve Markgraf - Distinguished FPGA Design & Support Engineer E5-E
www.designlinxhs.com

View solution in original post

os177
Visitor
Visitor
931 Views
Registered: ‎05-22-2020
Renaming the module ports seems to have solved the "problem". Did not know, Vivado actually takes a closer look at the names
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joe306
Scholar
Scholar
564 Views
Registered: ‎12-07-2018

Hello, I had the same problem. It took some time to fix it. I changed the name a few times and then was able to right click on the pin and change the type to Active High to match the type of the Auroro IP reset_pd pin.

Joe

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