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Registered: ‎09-14-2017

Can't program FPGA because previous design is wrong and it now hinders the SPI unit

Dear all,

 

I've got the following problem: when the system is turned on, the FPGA, artix 7, is configured correctly through a SPI flash which contains a bitstream previously loaded (when the design of the FPGA was correct). As the new design is wrong, after this first initialization, the FPGA cannot be programmed again. I also cannot use a JTAG to reprogram it, as I am on a custom system.

 

In fact, the FPGA is in between the processor, which orders to re/program the FPGA, and the SPI. Thus, no direct communication is allowed between the processor and the SPI.

 

My question is therefore: how do I bring the FPGA at the same state that it is found when programmed at start up time?

 

I've tried to study UG470 (https://www.xilinx.com/support/documentation/user_guides/ug470_7Series_Config.pdf) and XAPP586 (https://www.xilinx.com/support/documentation/application_notes/xapp586-spi-flash.pdf), but I could not find an answer.

 

Thank you very much

Giovanni

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Voyager
Voyager
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Registered: ‎06-24-2013

Re: Can't program FPGA because previous design is wrong and it now hinders the SPI unit

Hey Giovanni,

 

how do I bring the FPGA at the same state that it is found when programmed at start up time?

That really depends on what FPGA pins are available to the processor.

 

For example, with control over the mode pins, you can easily prevent an SPI boot.

 

Best,

Herbert

-------------- Yes, I do this for fun!
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