cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
muellera
Adventurer
Adventurer
242 Views
Registered: ‎02-22-2016

Can the clock from STARTUPE3 be used to drive ICAPE3

Hello,

the Ultrascale+ FPGA primitive STARTUPE3 provides a clock on a output port called CFGMCLK. This clock is generated by an internal oscillator and has a +-15% tolerance according to the Ultrascale+ device family data sheet.
Can this clock be used to drive the clock input on ICAPE3?
I could not find any information about the quality of the clock signal required by ICAPE3.

My aim is to use PCIe Tandem / PR, and if CFGMCLK could be used to drive ICAPE3 it would save an on-board oscillator and slim down the stage 1 bitstream.

Before continuing this path I would like to get confirmation that the quality of CFGMCLK is no issue for ICAPE3.

Thanks and kind regards,
/mu

0 Kudos
2 Replies
iguo
Xilinx Employee
Xilinx Employee
174 Views
Registered: ‎08-10-2008

ICAP itself can make use of FPGA internal oscillator directly; since the internal clock has a big tolerance, we never recommend you use it for PR. As for Tandem, it uses MCAP.

------------------------------------------------------------------------------------------------------------
Don't forget to reply, kudo, and accept as solution.
---------------------------------------------------------------------------------------------------------
muellera
Adventurer
Adventurer
150 Views
Registered: ‎02-22-2016

Thank you @iguo.
PR aside (you say you do never recommend this in the PR case), if ICAP uses the internal oscillator itself, it should be okay to drive the CLK pin of ICAP using CFGCLK as provided by USR_ACCESSE2.
Tandem with MCAP does not support DMA, therefor the goal is to use ICAP.

 

 

 

-- ...
-- csib and cfg_data_in are clocked by cfgclk.

icape3_inst : ICAPE3
    generic map (
      DEVICE_ID => X"ABCDEF00",
      ICAP_AUTO_SWITCH => "DISABLE",
      SIM_CFG_FILE_NAME => "NONE"
    )
    port map (
      AVAIL   => available,
      CLK     => cfgclk,
      CSIB    => csib,
      I       => cfg_data_in,
      O       => cfg_data_out,
      PRDONE  => prdone,
      PRERROR => prerror,
      RDWRB   => rdwrb
    );

  -- Primitive to get access to CFGCLK (internal oscialltor 50 MHz +- 15%).
  usr_accesse2_inst : USR_ACCESSE2
    port map (
      CFGCLK    => cfgclk,
      DATA      => open,
      DATAVALID => open
    );

 

 

 

0 Kudos