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Contributor
Contributor
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Registered: ‎11-06-2018

Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Hi all,

I'm using a VCU118 board, and trying to do a project that let multiple bitstreams time-share a certain PR region. I'm new to this area and been stuck here for a while.

My question is: can we use ICAP to readback the bitstream, and then use this readback bitstream to re-program the same area? If not, why?

Any comments are appreciated!  Thank you!

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Xilinx Employee
Xilinx Employee
320 Views
Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Theoratically, if you add the correct commands and put them in right format, yes you can do that.

But why? Why you want to reprogram the device with readback data? If you want to do Partial, please follow the Partial Reconfiguration guildlines - UG909, that makes all much easier.

If you are planning to do scrubbing or something else, you may need to contact a local support for some more inforamtion regarding this topic.

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Xilinx Employee
Xilinx Employee
354 Views
Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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A 'normal' bit file needs to contain commands to program FPGA or a certain part of it. But the one you readback are pure Configuration data. So you cannot use it to re-program FPGA directly.

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Contributor
Contributor
349 Views
Registered: ‎11-06-2018

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Hi @iguo,

Thank you for your reply! I'm aware that we need to pack commands into a bit file and then pass to ICAP.

For this particular case, can we replace the FDRI write area within the original bitstream with the readback Configuration Data that was masked with MSK file, and then re-program? Will this work?

 

The above mechanism is described by UG570  Page 190 Figure 10-3 to verify the readback data. So I was wondering if we can use the same mechasnim to "construct" a new bitstream that is useable
Screenshot from 2019-10-21 20-23-37.png

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Theoratically, if you add the correct commands and put them in right format, yes you can do that.

But why? Why you want to reprogram the device with readback data? If you want to do Partial, please follow the Partial Reconfiguration guildlines - UG909, that makes all much easier.

If you are planning to do scrubbing or something else, you may need to contact a local support for some more inforamtion regarding this topic.

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Don't forget to reply, kudo, and accept as solution.
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Contributor
Contributor
311 Views
Registered: ‎11-06-2018

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Hi @iguo,


One piece of my current project involves "preemptive scheduling" and be able to time-share the FPGA. To be specific, I want to do the following (Suppose we have Bit1 and Bit2, and they both run on PR region R1):

  • Schedule the initial Bit1 onto R1
  • After sometime, readback the Bit1 bitstream and save the Bit1_readback into DRAM
  • Schedule the initial Bi2 onto R1
  • After sometime, readback the Bi2 bitstream and save the Bit2_readback into DRAM
  • Schedule the Bit1_readback again onto R1

 

Just to be sure, you mean theorically its possible to do constrcut the above Bit1_readback using the readback data stream? Other than adding proper commands, is there anything else I should pay attention to?


Thank you so much for your responses, it helps a lot.

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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I don't know if there is any other potential risks as I never test this nor dig into this; but you need to be very famliar with Xilinx bitfile format; meanwhile, manually modifying bitstream is never encouraged as it's actually very dangerous. 

So you must retain whole Bit1 status and next time when you restart Bit1, you must start at the previous stopping point right? If this is the case, yes Partial cannot achieve this.

Can you clarify what parameters should be reserved during different iterations? Can you save these key info of Bit1 or Bit2 out of the PR region? Such as a BRAM? That's much easier.

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Contributor
Contributor
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Registered: ‎11-06-2018

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Hi @iguo,

 

>So you must retain whole Bit1 status and next time when you restart Bit1, you must start at the previous stopping point right?

Yes, we want to restart Bit1 from the previous stopping point.

 

> Can you clarify what parameters should be reserved during different iterations? Can you save these key info of Bit1 or Bit2 out of the PR region? Such as a BRAM?

Contents such as LUT RAM. The simplest example is a small "counter" IP which only has a counter insider and the counter is not using outside BRAM. A preemptive scheduling could preserve the counter value across multiple context swtiches.

 

> I don't know if there is any other potential risks as I never test this nor dig into thi

Is there a possibility to cause permanent harm to the chip? If possible, can you connect me to some folks who have used this before? Thank you, appreciate your reply

 

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Xilinx Employee
Xilinx Employee
219 Views
Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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If you incorrectly modify the bitstream and write something to a wrong destination, there is a POSSIBILITY that device get broken. 

This is definitely not a question can be solved on forum, and we never supports this, and it will take some or much effort. Please contact your local support, they will evaluate your project and then they can give you further suggestion. 

I personally still suggest you use a work around, like save the counter value out of PR region before Reconfiguration, and then read it back.

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Contributor
Contributor
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Registered: ‎11-06-2018

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Thank you @iguo. It's a reseach project, so I will mostly have to try it. I will be careful about it. I think you've shared enough information, thus I will accept one of you answer as the solution.


On a different aspect, I also have a quick question about the generated MSK file (.msk). The description about MSK is: "this file determines which bits in the bitstream should be compared to the readback data for verification purpose. If a mask bit is 1, that bit should not be verified". My question is: for the bits that should not be verified, do they represent those dynamic changing states in the readback data? For instance, the counter value should be mapped to those bits? 

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Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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yes, your understanding is correct.

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Contributor
Contributor
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Registered: ‎11-06-2018

回复: Can we use the readback bitstream to re-program the PR region (Ultrascale+ device)?

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Hi @iguo ,

 

Sorry to bug you one more time. Can I ask few more questions about the readback frame? I have some confusions about the readback verify and readback capture's capability.

 

Here it goes:

- Is the frame format of the readback data same with the initial configuration bitstream if I use the methods described by "Configuration Memory Read Procedure (SelectMAP)"?

- If the format is the same, is everything being readback? For example, assume the application never actually runs after the initial configuration bitstream was configured, will the readback frame data be exactly the same as the initial bitstream? If not, what would be missing? (excluding header info, just frame data).

- UG570 and xapp1230 mentioned we need to enable the CAPTURE[23] in the Control Register to enable the Readback Capture model. Will there be more data in the readback frame if I enable this?

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