cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Adventurer
Adventurer
180 Views
Registered: ‎03-28-2020

Check bits inside Bitstream ?

Jump to solution

Does Bitstream (including global Bitstream and partially reconfigurable Bitstream) have check bits inside these files?

We are trying to transmit bitstream files through an unattended, heavily interfered channel. According to previous tests, most of the data transmitted by this channel will have bit errors. Can such a channel be used to directly transmit the bitstream file configured by the FPGA? If the data is damaged during transmission, how can we identify the error code and try to repair it? Is there such a mechanism in the bitstream files directly generated by Vivado?

Tags (1)
0 Kudos
1 Solution

Accepted Solutions
Highlighted
125 Views
Registered: ‎01-22-2015

@wuyouniyanhu 

Does Bitstream (including global Bitstream and partially reconfigurable Bitstream) have check bits inside these files?

Yes.  They are called Cyclic Redundancy Check (CRC) bits and they are used by the FPGA to determine if the bitstream has been corrupted - as described on page 153 of UG570(v1.13).  If the CRC check fails then the FPGA aborts configuration.  The FPGA cannot use the CRC bits to correct errors in the bitstream.

 

We are trying to transmit bitstream files through an unattended, heavily interfered channel. According to previous tests, most of the data transmitted by this channel will have bit errors. Can such a channel be used to directly transmit the bitstream file configured by the FPGA?

No, at least not directly.  You could use a special transmitter and receiver on each end of the interfered channel.  In theory (Claude Shannon), the transmitter can encode the bitstream in such a way that it can be received/decoded error-free (with high probability) at the receiver.  The receiver can then send the decoded bitstream to the FPGA.

Another option is the develop an ethernet/LAN connection to the FPGA.  Ethernet/LAN connections typically have very low Bit Error Rate (BER). The bitfile is then sent from a remote computer to the FPGA and the FPGA then writes the bitfile to the configuration flash memory on the board. Then, the FPGA can be triggered to reconfigure itself from flash.  This method works well when combined with FPGA Multiboot (see Chapter 11 in UG570).

Cheers,
Mark

 

 

View solution in original post

1 Reply
Highlighted
126 Views
Registered: ‎01-22-2015

@wuyouniyanhu 

Does Bitstream (including global Bitstream and partially reconfigurable Bitstream) have check bits inside these files?

Yes.  They are called Cyclic Redundancy Check (CRC) bits and they are used by the FPGA to determine if the bitstream has been corrupted - as described on page 153 of UG570(v1.13).  If the CRC check fails then the FPGA aborts configuration.  The FPGA cannot use the CRC bits to correct errors in the bitstream.

 

We are trying to transmit bitstream files through an unattended, heavily interfered channel. According to previous tests, most of the data transmitted by this channel will have bit errors. Can such a channel be used to directly transmit the bitstream file configured by the FPGA?

No, at least not directly.  You could use a special transmitter and receiver on each end of the interfered channel.  In theory (Claude Shannon), the transmitter can encode the bitstream in such a way that it can be received/decoded error-free (with high probability) at the receiver.  The receiver can then send the decoded bitstream to the FPGA.

Another option is the develop an ethernet/LAN connection to the FPGA.  Ethernet/LAN connections typically have very low Bit Error Rate (BER). The bitfile is then sent from a remote computer to the FPGA and the FPGA then writes the bitfile to the configuration flash memory on the board. Then, the FPGA can be triggered to reconfigure itself from flash.  This method works well when combined with FPGA Multiboot (see Chapter 11 in UG570).

Cheers,
Mark

 

 

View solution in original post