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Visitor
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Registered: ‎04-07-2020

Clock-capable pins for single-ended inputs

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Hi,

Working on a board design using the Zynq XC7Z014SC-CLG400. The MRCC and SRCC pins seem to come in differential pairs  (e.g., IO_L11P_T1_SRCC_34 and IO_L11N,  IO_L12P_T1_MRCC_34 and IO_L12N, etc.).

If I want to use them as single-ended inputs, are there any restrictions on their use?  In particular, can I use the + and ‒ signals of a pair (for example, IO_L11P and IO_L11N) as two independent single-ended clock inputs?

The manual doesn't say anything (as far as I can tell), but I've seen other FPGAs where only the + input of a differential clock-capable input can be used as single-ended clock-capable input.

Thanks,
Cal-linux
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Registered: ‎01-22-2015

Re: Clock-capable pins for single-ended inputs

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@Cal-linux 

For the PL-side of your Zynq:

Clock-capable input pins usually come in pairs which have a P-side and an N-side.  Clock capable pins are special because they have dedicated routing to the FPGA clocking resources.  Using these dedicated routes for clocks is sometimes necessary for helping your design pass timing analysis.

For your device, there is only one dedicated route for each clock-capable pin pair.  Your clock input will be placed on the dedicated route if you use both pins (differential input) or if you use only the P-side pin (single-end input).

If you use only the P-side pin of a clock-capable pin pair, then you can use the N-side for general-purpose IO (ref page 31 of UG472(v1.14))  You could even send a clock input to the N-side pin.  However, because the clock input on the P-side pin is already using the dedicated routing, the clock input on the N-side pin cannot use the dedicated routing – and will instead be routed through the FPGA fabric.  Routing a clock through the FPGA fabric is usually bad for timing analysis reasons.

There is no such thing as clock-capable output pins.  That is, clocks can be sent out any general-purpose IO pin of the FPGA.  However, for timing analysis (and other) reasons, we typically use the ODDR as a kind of dedicated route when sending clocks out of the FPGA (ref Fig 2-18 in UG903(v2019.2)).

Mark

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Re: Clock-capable pins for single-ended inputs

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Hi @Cal-linux ,

Here also, you need to use only the + input of a differential clock-capable input  as single-ended clock-capable input.

Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
188 Views
Registered: ‎03-07-2018

Re: Clock-capable pins for single-ended inputs

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Hello @Cal-linux 

When input clock assigned to a negative pin or "N" pin, you will get DRC error/warning. Even if you are able to connect N pin to clock without any issues, it will not use dedicated clock resources. Only the P-side of a clock capable IO has dedicated clock routing resources. 

This is not applicable to output clock pin selection, so you should be able to drive a single-ended clock out of an "P" or "Npin.

 

Regards,
Bhushan

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Registered: ‎01-22-2015

Re: Clock-capable pins for single-ended inputs

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@Cal-linux 

For the PL-side of your Zynq:

Clock-capable input pins usually come in pairs which have a P-side and an N-side.  Clock capable pins are special because they have dedicated routing to the FPGA clocking resources.  Using these dedicated routes for clocks is sometimes necessary for helping your design pass timing analysis.

For your device, there is only one dedicated route for each clock-capable pin pair.  Your clock input will be placed on the dedicated route if you use both pins (differential input) or if you use only the P-side pin (single-end input).

If you use only the P-side pin of a clock-capable pin pair, then you can use the N-side for general-purpose IO (ref page 31 of UG472(v1.14))  You could even send a clock input to the N-side pin.  However, because the clock input on the P-side pin is already using the dedicated routing, the clock input on the N-side pin cannot use the dedicated routing – and will instead be routed through the FPGA fabric.  Routing a clock through the FPGA fabric is usually bad for timing analysis reasons.

There is no such thing as clock-capable output pins.  That is, clocks can be sent out any general-purpose IO pin of the FPGA.  However, for timing analysis (and other) reasons, we typically use the ODDR as a kind of dedicated route when sending clocks out of the FPGA (ref Fig 2-18 in UG903(v2019.2)).

Mark

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