UPGRADE YOUR BROWSER

We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

cancel
Showing results for 
Search instead for 
Did you mean: 
Highlighted
Visitor wyattlaw4
Visitor
409 Views
Registered: ‎11-29-2019

Clock error

Jump to solution

Hello,

I made a simple addition caluclator in Vivado and am using a Basys3 FPGA board. All of the code works correclty except for the constraint code giving me this error:

[Place 30-574] Poor placement for routing between an IO pin and BUFG. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Add_IBUF] >

Add_IBUF_inst (IBUF.O) is locked to IOB_X0Y15
and Add_IBUF_BUFG_inst (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0

 

I add in set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets Add_IBUF] and it wont synthesize saying that set_porperty expects at least one obejct. What would fix this?

0 Kudos
1 Solution

Accepted Solutions
61 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

Wyatt,

From the VHDL, it looks like AC is supposed to be a clock input to the FPGA.  A clock is a digital signal that toggles periodically between low and high. 

Your design currently works as follows:  If reset=0 and Add=1 then a new addition is performed every time that AC toggles from low-to-high.  So, make sure that you are toggling the AC input during testing. 

If you did not want AC to be a clock then you must rewrite your VHDL to account for the new meaning of AC.

Mark

View solution in original post

0 Kudos
9 Replies
368 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

@wyattlaw4 

Welcome to the Xilinx Forum!

I think you have simply made a typo.  Try the following version of the constraint:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets -of [get_pins {Add_IBUF_inst/O}]] 

It is important to understand why you are being asked to use this constraint and the disadvantages of using this constraint.  For this information please see Table 3-4 (and pages near this Table) in UG949 (v2019.1).

Cheers,
Mark

0 Kudos
Visitor wyattlaw4
Visitor
355 Views
Registered: ‎11-29-2019

Re: Clock error

Jump to solution

Thanks for the reply, it still gives the same error when trying to synthesize saying that set_property expects at least one object

0 Kudos
310 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

@wyattlaw4 

The error you are getting for set_property indicates that we’re using the wrong name for the net coming out of the IBUF in your design. 

One way to get the correct name for this net is to do the following:

  • Comment out the set_property constraint
  • Run Synthesis
  • Open Synthesized Design
  • In the Vivado Tcl Console, try each of the following commands.  
get_nets *IBUF*
-or-
get_nets *Add_IBUF*

These commands will give you a list of net names, from which you can pick the net name associated with your IBUF (which should look something like "..Add_IBUF..").

For example, in the screenshot below, I've used the command, get_nets *IBUF*, and have gotten a list of two names, (CLK1_IN_IBUF and RST_IN_IBUF).
get_nets.jpg

Once you find the correct name of the net (eg. my_net_correct_name), then use it in the set_property command as follows:

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets my_net_correct_name]

If that doesn't work, then attach an archive of your project to your next post - and I'll take a look at it.  To archive a Vivado project, use the menu selections (File > Project > Archive).

Mark

Visitor wyattlaw4
Visitor
276 Views
Registered: ‎11-29-2019

Re: Clock error

Jump to solution

Mark,

Thank you for the reply. I tried a couple of the names that it gave me and they all give the same error. I talked to some friends and they all just used the IBUF name that it told them to use down in the messages.  For me it gives the same error, and trying the differnt names also does. I have attached an archieve of the project. Thank you for taking time to look at it, I really appreciate it.

0 Kudos
191 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

@wyattlaw4 

Your VHDL made Vivado think that input, "Add", was a clock.  Clocks should only enter the FPGA on a clock-capable pin.  Since "Add" was entering the FPGA on a pin that was not clock-capable, then you were getting the CLOCK_DEDICATED_ROUTE warnings.

I don't think you wanted "Add" to be a clock.  If you write your VHDL process as shown below, then Vivado will not think "Add" is a clock and the CLOCK_DEDICATED_ROUTE warnings should disappear.

 process(AC, reset, Add) 
   begin 
     if rising_edge(AC) then
       if (reset='1') then
         reg_out <= "00000000"; 
       elsif (Add='1') then
         reg_out <= A_8bit + B_8bit;
       end if;
     end if; 
 end process; 

Good luck with your studies,
Mark

0 Kudos
Visitor wyattlaw4
Visitor
165 Views
Registered: ‎11-29-2019

Re: Clock error

Jump to solution

Mark,

Thank you for your help. That makes sense. I replaced that part of my code with yours. For some reason, I still get the error saying the set_property expects at least one object when trying to implement the constraint file. I looked in the synthesized design and tried a couple of the given IBUF commands and also the original one that Vivado suggested. Did it work for you?  Any ideas?

Thank you so much,

Wyatt

0 Kudos
144 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

Wyatt,

In your design, it seems that you want input, AC, to be a clock.  This input is not coming from a clock-capable pin of the FPGA.  Hence, you are getting the CLOCK_DEDICATED_ROUTE warning.

Your project should run thru synthesis and implementation without error if you use the following constraints in the xdc-file:

create_clock -period 20.0 [get_ports {AC}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {AC_IBUF}]

The create_clock constraint is needed for clock inputs.  The create_clock constraint shown above tells Vivado that your clock, AC, has a period of 20ns.

You may still get a critical warning, "..expects at least one object ", about the set_property constraint during synthesis.  However, implementation sees the set_property constraint as valid.  So, I think you can ignore the synthesis warning.

Mark

0 Kudos
Visitor wyattlaw4
Visitor
102 Views
Registered: ‎11-29-2019

Re: Clock error

Jump to solution

Mark,

That helps. It allowed me to synthesize it and bypass the error and was able to implement it. Once it's on the board, nothing happens. Would you mind seeing if there are any obvious errors that may be causing this? I really appreciate your help and I have checked thrugh everything and think I'm missing something that another set of eyes may find. Does the code look like it should work as is? 

Thank you so much,

Wyatt

0 Kudos
62 Views
Registered: ‎01-22-2015

Re: Clock error

Jump to solution

Wyatt,

From the VHDL, it looks like AC is supposed to be a clock input to the FPGA.  A clock is a digital signal that toggles periodically between low and high. 

Your design currently works as follows:  If reset=0 and Add=1 then a new addition is performed every time that AC toggles from low-to-high.  So, make sure that you are toggling the AC input during testing. 

If you did not want AC to be a clock then you must rewrite your VHDL to account for the new meaning of AC.

Mark

View solution in original post

0 Kudos