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Registered: ‎04-01-2019

Clock generation constrains using Zynq 7000 Z7015

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Hi everyone .

I'm searching for a document that decribes IO Tr,Tf ,Jitter constrains for Zynq 7000 Z015 series.

In my project i'm using quad simultaneous sampling ADC with 2MSPS.(LTC2324-12)

The clock requirements for maximum ability is:

CMOS - 55[MHz] for DDR or 110[MHz] for SDR.

LVDS - 150[MHz] for DDR ot 300[MHz] for SRD.

If i want to generate the clock using the SoC i need to know the abilty of each IO standard.

Thank you.

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Registered: ‎01-22-2015

Re: Clock generation constrains using Zynq 7000 Z7015

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@bsshlomy 

I understand that you want to use the Zynq 7000 to generate the input clock, SCK, for your high-speed ADC, LTC2324-12.

For high-speed ADCs, using an FPGA-produced clock for SCK is not recommended because the high jitter on FPGA-produced clocks can degrade the Effective Number Of Bits (ENOB) for the ADC.  Instead, you should purchase a low-jitter clock generator and use it to create SCK for your ADC.

Clocks on the PL side of the Zynq are often created by the MMCM clocking module that is setup using the Xilinx Clocking Wizard IP (see Xilinx document, PG065). The jitter on the MMCM output clocks can be immediately seen in the “Summary” tab of the Clocking Wizard.

clkwiz_jitter.jpg

As you say, the IOSTANDARDs of LVDS and LVCMOS can be used to send the MMCM-produced clocks out of the FPGA.  You have asked for Tr/Tf of these IOSTANDARDs, which you will not find in any of the Xilinx documents.  This is because Tr/Tf depends on many factors as described in the following post. 

https://forums.xilinx.com/t5/Implementation/Maximum-speed-of-LVCMOS-I-O/m-p/707633#M15677


However, the clock speeds for LVCMOS and LVDS that you have mentioned are achievable.  See the following post for more information.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Comparison-of-I-O-standards-and-recommended-uses/m-p/854589#M26802


Finally, you have a “source synchronous input” interface between the LTC2324-12 ADC and the FPGA.  That is, the ADC will send both a data clock, CLKOUT, and data to the FPGA.  CLKOUT will have the same frequency as the ADC input clock, SCK.  You will need to write timing constraints for this ADC-to-FPGA interface and ensure that it passes Vivado timing analysis.  You will find information about “source synchronous input” interfaces in the following post.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/LVDS-DDR-input-constrains/m-p/693833

Cheers,
Mark

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122 Views
Registered: ‎01-22-2015

Re: Clock generation constrains using Zynq 7000 Z7015

Jump to solution

@bsshlomy 

I understand that you want to use the Zynq 7000 to generate the input clock, SCK, for your high-speed ADC, LTC2324-12.

For high-speed ADCs, using an FPGA-produced clock for SCK is not recommended because the high jitter on FPGA-produced clocks can degrade the Effective Number Of Bits (ENOB) for the ADC.  Instead, you should purchase a low-jitter clock generator and use it to create SCK for your ADC.

Clocks on the PL side of the Zynq are often created by the MMCM clocking module that is setup using the Xilinx Clocking Wizard IP (see Xilinx document, PG065). The jitter on the MMCM output clocks can be immediately seen in the “Summary” tab of the Clocking Wizard.

clkwiz_jitter.jpg

As you say, the IOSTANDARDs of LVDS and LVCMOS can be used to send the MMCM-produced clocks out of the FPGA.  You have asked for Tr/Tf of these IOSTANDARDs, which you will not find in any of the Xilinx documents.  This is because Tr/Tf depends on many factors as described in the following post. 

https://forums.xilinx.com/t5/Implementation/Maximum-speed-of-LVCMOS-I-O/m-p/707633#M15677


However, the clock speeds for LVCMOS and LVDS that you have mentioned are achievable.  See the following post for more information.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/Comparison-of-I-O-standards-and-recommended-uses/m-p/854589#M26802


Finally, you have a “source synchronous input” interface between the LTC2324-12 ADC and the FPGA.  That is, the ADC will send both a data clock, CLKOUT, and data to the FPGA.  CLKOUT will have the same frequency as the ADC input clock, SCK.  You will need to write timing constraints for this ADC-to-FPGA interface and ensure that it passes Vivado timing analysis.  You will find information about “source synchronous input” interfaces in the following post.

https://forums.xilinx.com/t5/Other-FPGA-Architecture/LVDS-DDR-input-constrains/m-p/693833

Cheers,
Mark

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Registered: ‎04-01-2019

Re: Clock generation constrains using Zynq 7000 Z7015

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Hi Mark.

Thank you for a such elaborate answer.

I will add a low jitter clock to my design just to be on the safe side.

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