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Contributor
Contributor
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Registered: ‎11-09-2018

Clocking in FPGA

What are the clocking resources in 7 series FPGA?

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5 Replies
Adventurer
Adventurer
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Registered: ‎06-28-2018

Re: Clocking in FPGA

I am sure there are a lot of forum posts and Xilinx documents where you can find the information you're looking for.

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Explorer
Explorer
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Registered: ‎06-25-2014

Re: Clocking in FPGA

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Contributor
Contributor
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Registered: ‎11-09-2018

Re: Clocking in FPGA

What is meant by Global clock network, Regional clock network and I/O clock network and what are differences? what are the function? How it works?

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Adventurer
Adventurer
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Registered: ‎06-28-2018

Re: Clocking in FPGA

esakki@babu

You are the laziest person I have ever seen on this forum. Is reading some documents so hard for you?

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Scholar u4223374
Scholar
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Registered: ‎04-26-2015

Re: Clocking in FPGA

esakki@babu 

 

Global clock network means that it's worldwide. The global clock network is linked to all Xilinx 7-series FPGAs and SoCs (eg. Zynq), as well as selected Intel/Altera models (the Cyclone V family supports it, I think). This allows a clock to be shared between projects that are separated by very large distances, greatly easing communication. Note that while the clock network exists worldwide, access to it is restricted in countries that the USA is currently unfriendly towards (eg. Iran, Cuba, Belgium, North Korea). My understanding is that it's driven by the globally-available GPS clock signal.

 

The regional clock network is, as the name implies, regional. It's shared between devices on the same continent, with the exception of Eurasia (Europe and Asia are considered separate regions by Xilinx). Because global network resources are limited, you would normally use the regional network for most tasks unless you actually need the global one. The local nature allows it to take advantage of GPS WAAS (wide area augmentation system) for even higher accuracy than the global network can provide.

 

The I/O clock network is connected to the Internet (that's the "I") to allow for local and (high-latency) overseas (that's the "O") clocking. Because it's pretty simple technology, the I/O clock network can be used anywhere - but you have to live with its restrictions (eg. if the internet fails, so does your FPGA clock). I would normally avoid the I/O clock network if possible. Implementation is very simple; the clock is distributed by NIST servers, the same ones that Windows uses to keep its clock up-to-date.

 

I hear that Xilinx and Intel are teaming up to develop a "Solar clock network" in time for SpaceX's proposed colonisation of Mars, to ensure that FPGAs work correctly there when the first Starship touches-down. Considering the large (and variable) light-speed delay between the Earth and Mars, this is likely to be quite a challenge - but one that I'm sure these two companies can overcome.

 

... Or you could read UG472 that was linked above, and learn the real answers to your questions.