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Adventurer
Adventurer
1,315 Views
Registered: ‎11-30-2008

Configuration error: Virtex 5 with XCF128X Flash, In-direct ISP, BPI-Up Mode

Hi Community,

We can't seem to download the mcs file to the flash rom (XCF128X) using the in-direct ISP in BPI-Up mode. Can somebody please confirm what the mode settings are during the in-direct ISP? Should it be set to BPI-Up Mode or the JTAG mode? We are setting it to BPI-Up mode during in-direct ISP. And copied below are the messages during the in-direct ISP.

Please help how to resolve the issue.
Thanks.

Selected part: XCF128X
// *** BATCH CMD : attachflash -position 1 -bpi "XCF128X"
// *** BATCH CMD : assignfiletoattachedflash -position 1 -file "D:/05. ISE work/ML9003/ML9003 for LX155/ML9003_LX155_2M.mcs"
INFO:iMPACT - Current time: 2018-02-07 11:58:06 PM
// *** BATCH CMD : Program -p 1 -dataWidth 16 -rs1 NONE -rs0 NONE -bpionly -e -v -loadfpga
PROGRESS_START - Starting Operation.
Maximum TCK operating frequency for this device chain: 33000000.
Validating chain...
Boundary-scan chain validated successfully.
1: Device Temperature: Current Reading: -273.00 C
1: VCCINT Supply: Current Reading: 0.000 V
1: VCCAUX Supply: Current Reading: 0.000 V
'1': BPI access core not detected. BPI access core will be downloaded to the device to enable operations.
INFO:iMPACT - Downloading core file C:/Xilinx/14.7/LabTools/LabTools/virtex5/data/xc5vlx155_jbpi.cor.
'1': Downloading core...
Match_cycle = NoWait.
Match cycle: NoWait
LCK_cycle = NoWait.
LCK cycle: NoWait
done.
INFO:iMPACT:2219 - Status register values:
INFO:iMPACT - 0011 1111 0101 1110 0000 1000 0100 0000
INFO:iMPACT:2492 - '1': Completed downloading core to device.
Current cable speed is set to 3.000 Mhz.
Setting Flash Control Pins ...
Setting Configuration Register ...
Populating BPI common flash interface ...
Common Flash Interface Information Query completed successfully.
INFO:iMPACT - Common Flash Interface Information from Device:
INFO:iMPACT - Verification string: 51 52 59
INFO:iMPACT - Manufacturer ID: 49
INFO:iMPACT - Vendor ID: 01
INFO:iMPACT - Device Code: 18
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Erasing device...
'1': Start address = 0x00000000, End address = 0x004E4AFF.
done.
'1': Erasure completed successfully.
Setting Flash Control Pins ...
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
INFO:iMPACT - Using Word Programming.
'1': Programming Flash.
done.
Setting Flash Control Pins ...
'1': Flash Programming completed successfully.
Using x16 mode ...
Setting Flash Control Pins ...
Setting Configuration Register ...
'1': Reading device contents...
done.
'1': Verification completed.
Setting Flash Control Pins ...
'1': Configuration data download to FPGA was not successful. DONE did not go high, please check your configuration setup and mode settings.
PROGRESS_END - End Operation.
Elapsed time = 605 sec.
-- ace
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5 Replies
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Scholar
Scholar
1,312 Views
Registered: ‎02-27-2008

MCS file is an ancient format,

 

Not used for any direct to FPGA programming (only used by microprocessors which convert the MCS file then program the FPGA's in their raw binary format).


Use the .bin or .bit file instead. (one has a prefix of the part, the other doesn't -- both are raw binary files used to program the bitstream).

 

 

Austin Lesea
Principal Engineer
Xilinx San Jose
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Adventurer
Adventurer
1,275 Views
Registered: ‎11-30-2008

Hello Austin, thanks for the reply. We tried the .bit file and we can actually download it to the FPGA successfully. However we do need to get the EEPROM to work and have the EEPROM keep the mcs file for the FPGA configuration.

 

I have an additional question to make sure that our set-up is correct. Below is how we are power sequencing the power supplies for the FPGA and the Xilinx XCF128X EEPROM.

     Virter 5 LX155 FPGAs' VCCINT (1V)       = Sequence 0

     XCF128X EEPROMs' VDD (1.8V)           = Sequence 0   

     Virter 5 LX155 FPGAs' VCCAUX (2.5V)   = Sequence 1

     Virter 5 LX155 FPGAs' VCCO (3.3V)        = Sequence 3

     XCF128X EEPROMs' VDDQ/VPP (3.3V) = Sequence 3

So you see any issues with the above power sequence?

I appreciate your help.

-- ace
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Highlighted
Scholar
Scholar
1,248 Views
Registered: ‎02-27-2008

ace,

 

Any sequence works (part will configure, operate) unless that sequence is prohibited in the data sheet.  I do not recall any sequence is prohibited.  The sequence specified in the data sheet is used to get the currents specified.  A different sequence may have different max start current requirements (not much, just some).  The specified sequence is also that which the IO remain tristate, do not assert.  I also recall on V5 any sequence was OK for IO.

 

Not sure why you think you need the MCS file in the EEPROM, as the V5 is never going to read it.  So it must be there for some other reason?

 

https://forums.xilinx.com/t5/General-Technical-Discussion/MCS-Vs-BIN-file/td-p/69302

Austin Lesea
Principal Engineer
Xilinx San Jose
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Highlighted
Adventurer
Adventurer
1,233 Views
Registered: ‎11-30-2008

Hi Austin,

 

Thanks again for your reply. We finally found what was wrong with the design over the weekend. The clock was not properly set. So with that fixed, we can now download the firmware via the FPGA to the Flash using BPI-Up mode.

 

 

-- ace
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Highlighted
Scholar
Scholar
1,226 Views
Registered: ‎02-27-2008

Just curious,


What clock wasn't set?

Austin Lesea
Principal Engineer
Xilinx San Jose
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