02-08-2018 09:44 AM
02-08-2018 09:52 AM
MCS file is an ancient format,
Not used for any direct to FPGA programming (only used by microprocessors which convert the MCS file then program the FPGA's in their raw binary format).
Use the .bin or .bit file instead. (one has a prefix of the part, the other doesn't -- both are raw binary files used to program the bitstream).
02-08-2018 06:48 PM
Hello Austin, thanks for the reply. We tried the .bit file and we can actually download it to the FPGA successfully. However we do need to get the EEPROM to work and have the EEPROM keep the mcs file for the FPGA configuration.
I have an additional question to make sure that our set-up is correct. Below is how we are power sequencing the power supplies for the FPGA and the Xilinx XCF128X EEPROM.
Virter 5 LX155 FPGAs' VCCINT (1V) = Sequence 0
XCF128X EEPROMs' VDD (1.8V) = Sequence 0
Virter 5 LX155 FPGAs' VCCAUX (2.5V) = Sequence 1
Virter 5 LX155 FPGAs' VCCO (3.3V) = Sequence 3
XCF128X EEPROMs' VDDQ/VPP (3.3V) = Sequence 3
So you see any issues with the above power sequence?
I appreciate your help.
02-09-2018 06:58 AM
Any sequence works (part will configure, operate) unless that sequence is prohibited in the data sheet. I do not recall any sequence is prohibited. The sequence specified in the data sheet is used to get the currents specified. A different sequence may have different max start current requirements (not much, just some). The specified sequence is also that which the IO remain tristate, do not assert. I also recall on V5 any sequence was OK for IO.
Not sure why you think you need the MCS file in the EEPROM, as the V5 is never going to read it. So it must be there for some other reason?
02-12-2018 05:07 PM
Thanks again for your reply. We finally found what was wrong with the design over the weekend. The clock was not properly set. So with that fixed, we can now download the firmware via the FPGA to the Flash using BPI-Up mode.
02-13-2018 07:32 AM
What clock wasn't set?