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altde
Observer
Observer
5,826 Views
Registered: ‎05-16-2011

Configuration flash programming fails if the Artix-7 FPGA is configured.

We've run into a puzzling issue when trying to program a QSPI configuration flash using the Vivado hardware manager.  When the FPGA is unconfigured, flash programming works fine.  If the FPGA has been configured (from the programmed flash), trying to reprogram the flash fails.  Here's what's in the Tcl console for the failure (trying to just erase the flash produces the same errors):

set_property PROGRAM.ADDRESS_RANGE  {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.FILES [list "C:/Users/djpfeiff/FCHIC_TCTS/Type146_08312016_179-1247-002/niu_146_top.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.BLANK_CHECK  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.ERASE  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CFG_PROGRAM  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.VERIFY  1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CHECKSUM  0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
startgroup
if {![string equal [get_property PROGRAM.HW_CFGMEM_TYPE  [lindex [get_hw_devices xc7a200t_0] 0]] [get_property MEM_TYPE [get_property CFGMEM_PART [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]]]] }  { create_hw_bitstream -hw_device [lindex [get_hw_devices xc7a200t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7a200t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7a200t_0] 0]; };
INFO: [Labtools 27-3164] End of startup status: HIGH program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
ERROR: [Labtools 27-3347] Flash Programming Unsuccessful: Failure to set flash parameters. ERROR: [Common 17-39] 'program_hw_cfgmem' failed due to earlier errors.

If the FPGA is not configured, flash programming works.  The Tcl commands are all the same, but the last few status messages are different:

INFO: [Labtools 27-3164] End of startup status: HIGH
program_hw_devices: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1347.727 ; gain = 0.000
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
Mfg ID : 20   Memory Type : ba   Memory Capacity : 19   Device ID 1 : 0   Device ID 2 : 0
Performing Erase Operation...
Erase Operation successful.
Performing Program and Verify Operations...

(with some more successful-looking lines after that)

As far as we can tell, we're doing exactly the same thing except for the configuration status of the FPGA.  Do you have any ideas of what might be causing this?

It looks suspicious to me that the failing case doesn't have this line:

program_hw_devices: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 1347.727 ; gain = 0.000

But that might be a red herring, because both cases have the preceding "INFO" line, and when we reconfigure an already-configured FPGA (as opposed to trying to program its flash), it doesn't have that line but it does have the "INFO" line and it does appear to succeed.  On the other hand, we're reprogramming with the same bit file, so if the programmed image somehow prevents reprogramming, we wouldn't be able to identify a failure unless Vivado told us.  (I assume it would do that, but am not completely sure.)

I was initially suspicious that we might have accidentally changed PROGRAM.HW_CFGMEM_TYPE or PROGRAM.HW_CFGMEM (which are tested in the "if" at the beginning of the very long line before the "INFO"), but if we did that it doesn't show up in the Tcl console.

We're using Vivado 2018.2 (lab edition) with an Artix-7 FPGA (XC7A200T-2FB676I) and a Micron MT25QL256ABA quad-SPI flash.

Thanks,

Dan

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14 Replies
jg_bds
Scholar
Scholar
5,796 Views
Registered: ‎02-01-2013

When program_hw_devices runs successfully, you see the extra message. Since you don't see a success (or failure) message for that process when you experience a problem, it's possible that it's not running. If that process doesn't run (which is done to over-write the FPGA with a new bitfile that allows the configuration memory to be programmed) then there's no chance the memory programming will work.

You expressed a concern about the "if" condition failing--perhaps it is.

The check of the Startup Status could be returning 1 because the FPGA re-program sequence never started, so the Startup Status remains high since the original boot.

Do you see INIT go low when you try to re-program the FPGA?

It's possible that the operation of the FPGA is changing its environment, preventing it from being re-programmed.

Have you tried using a dummy FPGA image--one which affects no IO pins when it come up?

-Joe G.

wduffy
Xilinx Employee
Xilinx Employee
5,768 Views
Registered: ‎01-21-2013

Hi @altde,

I would second the idea from @jg_bds of trying a dummy FPGA image.

In the successful case, have you verified that the design is running as expected?

It looks like in the failing condition it doesn’t even start the process of trying to erase the device.

Something I noticed from your console output is that your setting for the erase is use_file. I would choose entire device. Probably not the root cause of the issue but something to be aware of.

It would be interesting to hear back on the programming of the dummy/simple design.

Thanks,
Wendy
Xilinx Technical Support
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altde
Observer
Observer
5,758 Views
Registered: ‎05-16-2011

Thanks, @jg_bds and @wduffy.

We'll look at some of those things when we get a chance (it's not our highest priority, since we can get around the problem by keeping the FPGA from configuring itself).

Does the specific message in that first error ("Failure to set flash parameters.") give us any clues?  I wasn't able to find anything about it in the documentation or forums.

Regards,

Dan

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hj
Moderator
Moderator
5,746 Views
Registered: ‎06-05-2013

Hi @altde

I just tried to reproduce this with KC705 board which has similar kind of flash( MT25ql128) but it works fine. 

Here is the snapshot:-

2018_2_prog.png 

Now there are few things which you should look for: 

1) Share the report_property -all [current_design] after you open the implemented design. 

# use current_design,

2) Share the hw server logs. To enable logs start HW server through command line with "-L- -lslave" option. use the below command. 

hw_server -L<log filename> -lslave

Share both the logs

--where you program the device first and program the flash next. 

-- When you program flash directly,without programming the device. 

To do this close Vivado HWM and make sure there is no hw_server.exe process running.  Start the Vivado TCL console from the start menu and then enter this command.  Once the hw_server is running open Vivado HWM and connect to this hs_server.  From here go through the erase/program process.  You should now see log information in the TCL console.  Send the log information to us. 

3) As shared by other experts try with some other simple design if you have any.

Thanks

Harshit

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altde
Observer
Observer
5,681 Views
Registered: ‎05-16-2011

Thanks, @hj.

As mentioned above, we have a temporary way around this (and lots of other stuff going on), so this is lower priority.  When we get back to it, we'll try the suggestions.

But there are two additional pieces of information I can provide now.

* Unfortunately we don't have access to the implemented design because it was developed by a third party and all we get is the bit file.

* One difference between your KC705 test and ours is that you programmed the FPGA from Vivado, while we let the FPGA configure itself from the flash and then tried to program the flash from Vivado.  I don't know if that matters, but it is a difference.

Thanks,

Dan

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hj
Moderator
Moderator
5,629 Views
Registered: ‎06-05-2013

@altde,

Thanks for the update. Those properties might be helpful here. If you don't have them then we can think of other ways.

I just tried to follow the below steps and it worked.

-- Power Up

-- mode pin to SPI

-- Program Flash

-- Used vivado option to boot from flash

-- Once FPGA is programmed tried again to program the flash. 

-- Power OFF board 

-- Power ON board. Let it boot from flash.

-- Programmed flash again

-- And it worked. !! 

Attached is the log. 

Thanks

Harshit

 

-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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dlock4
Newbie
Newbie
3,903 Views
Registered: ‎10-22-2020

Hi,

Somebody find a solution for this problem? i have the same problem and i would like to resolve.

For us we was using mt25ql256 with artix 7 on production floor.  The SPI serial eeprom was programmed using Xilinx 14.7 release.

Last week, production has changed the 256 by the mt25ql512 serial eeprom , who's is support only by vivado. Using Vivado_lab (2020.1), i develop a script to program the new serial eeprom.  The script work fine when the spi eeprom is not programmed but fail when the FPGA is programmed.

However, i'm able to program the mt25ql512 serial eeprom using Xilinx 14.7 ( set XIL_IMPACT_SKIPIDCODECHECK=1) without any problem.

The problem is software and related to vivado but i don't have the solution?

 

 

 

 

 

 

 

 

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hj
Moderator
Moderator
3,892 Views
Registered: ‎06-05-2013

@dlock4
Please share your script I can try to reproduce this on the Xilinx evaluation board.
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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dlock4
Newbie
Newbie
3,850 Views
Registered: ‎10-22-2020

Script working with Xilinx 14.7:

setlog -file ./fpgaprg.log
setMode -bscan
setCable -port auto
identify -inferir
identifyMPM
assignfile -p 1 -file ./FPGA_LOAD/carrier_fpga_top.bit
assignfile -p 2 -file ./PI7C9X2G404SL_modif.bsd
attachflash -position 1 -spi "N25Q256"
assignfiletoattachedflash -position 1 -file ./FPGA_LOAD/carrier_fpga_top.mcs
program -p 1 -dataWidth 4 -spionly -e -v -loadfpga
quit

Vivado Script who not working when FPGA is programmed:

open_hw_manager
connect_hw_server -allow_non_jtag
open_hw_target
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7a200t_0] 0] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.FILES [list "C:/fpga_top.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]

create_hw_bitstream -hw_device [lindex [get_hw_devices xc7a200t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7a200t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7a200t_0] 0]; refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]

 

 

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jg_bds
Scholar
Scholar
3,840 Views
Registered: ‎02-01-2013

 

When we design a board, we always provide a way to change the boot configuration of a device from its 'normal' mode to JTAG.

If possible, change your board so the Artix configuration mode is JTAG mode, and then check if you can re-program the already programmed flash.

If you can, then (most likely) Vivado is not properly re-initializing the flash--which had been used once since power-on to program the FPGA.

-Joe G.

 

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dlock4
Newbie
Newbie
3,832 Views
Registered: ‎10-22-2020

I will try to change the mode, as your suggestion.

However, why the serial flash programming work each time when i use Xilinx 14.7 and impact?

 

 

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jg_bds
Scholar
Scholar
3,825 Views
Registered: ‎02-01-2013

 

Based on your description of your efforts, my suspicion would be that ISE/iMPACT *did* properly re-initialize the flash before trying to program it.

(Not everything "newer" is "better".)

-Joe G.

 

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hj
Moderator
Moderator
3,772 Views
Registered: ‎06-05-2013


@dlock4 wrote:

Script working with Xilinx 14.7:

setlog -file ./fpgaprg.log
setMode -bscan
setCable -port auto
identify -inferir
identifyMPM
assignfile -p 1 -file ./FPGA_LOAD/carrier_fpga_top.bit
assignfile -p 2 -file ./PI7C9X2G404SL_modif.bsd
attachflash -position 1 -spi "N25Q256"
assignfiletoattachedflash -position 1 -file ./FPGA_LOAD/carrier_fpga_top.mcs
program -p 1 -dataWidth 4 -spionly -e -v -loadfpga
quit

Vivado Script who not working when FPGA is programmed:

open_hw_manager
connect_hw_server -allow_non_jtag
open_hw_target
current_hw_device [get_hw_devices xc7a200t_0]
refresh_hw_device -update_hw_probes false [lindex [get_hw_devices xc7a200t_0] 0]
create_hw_cfgmem -hw_device [lindex [get_hw_devices xc7a200t_0] 0] [lindex [get_cfgmem_parts {mt25ql512-spi-x1_x2_x4}] 0]
refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
set_property PROGRAM.ADDRESS_RANGE {use_file} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.FILES [list "C:/fpga_top.mcs" ] [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.PRM_FILE {} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.UNUSED_PIN_TERMINATION {pull-none} [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.BLANK_CHECK 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.ERASE 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CFG_PROGRAM 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.VERIFY 1 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]
set_property PROGRAM.CHECKSUM 0 [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]

create_hw_bitstream -hw_device [lindex [get_hw_devices xc7a200t_0] 0] [get_property PROGRAM.HW_CFGMEM_BITFILE [ lindex [get_hw_devices xc7a200t_0] 0]]; program_hw_devices [lindex [get_hw_devices xc7a200t_0] 0]; refresh_hw_device [lindex [get_hw_devices xc7a200t_0] 0]
program_hw_cfgmem -hw_cfgmem [ get_property PROGRAM.HW_CFGMEM [lindex [get_hw_devices xc7a200t_0] 0]]

 

 


I have tested this on the KCU105 board with the 2020.1 system edition. Failed to reproduce this. 

Attached is the log. 

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For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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dlock4
Newbie
Newbie
3,613 Views
Registered: ‎10-22-2020

Hi,

Have you toggle the power after programmation?

On my system, if i toggle the power to force FPGA to load config from serial eeprom, i unable to program again, using vivado

see attached log

 

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