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kevin_cdac
Visitor
Visitor
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Registered: ‎09-16-2020

Configuration of 7 Sereis FPGA in Master SPI mode

Hi,

I am planning to configure my Artix 7 FPGA in Master SPI mode. So can I use the Revision Select pins (RS1, RS0) as normal I/O or should it be left floating(unconnected)?

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iguo
Xilinx Employee
Xilinx Employee
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Registered: ‎08-10-2008

In SPI config mode, they are the same as other GPIOs and you can use them after configuration.

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kevin_cdac
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Registered: ‎09-16-2020

Thank you.

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