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Participant nawcadengineer2015
Participant
553 Views
Registered: ‎02-27-2018

Configure Kintex-7

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Hello team,

I'm trying to configure a kintex-7 through another FPGA. The Kintex-7 FPGA is setup as slave SelectMap x32 and all configuration pins such as cclk,program_b,init_b,csi_b,rdwr_b and done are connected to another FPGA. The software grabs the bitstream file and send to the main FPGA through pcie x4 lane. I have logic in the FPGA that handles programming data. I configure the K7 FPGA by first clear the fpga by set Program_B low. After that I keep rdwr_b low and toggle csi_b until Done line high but the Done line is never high.  Please be advise. BTW, the cclk is 100mhz. 

Thanks,

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Xilinx Employee
Xilinx Employee
512 Views
Registered: ‎06-13-2018

Re: Configure Kintex-7

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Hi @nawcadengineer2015 :

I believe you are using Free-Running CCLK method (by toggeling csi_b signal) for Non-continuous data loading.

selectMAPdata.PNG   

Few things I will suggest you to verify:

1. Confirm mode pins are set as M[2:0] = 110 for x32 Slave SlectMAP interface.

2. Make sure PROGRAM_B is connected to an external ≤ 4.7 kΩ pull-up resistor to VCCO_0 to ensure a stable High input, and it is recommended push-button to GND to enable manual configuration reset.

3. After the FPGA configuration is cleared (PROGRAM_B is pulsed Low), what is the status of INIT_B pin? This pin should be low when configuration is in reset state or when the FPGA is initializing (clearing) its configuration memory.  (Connect INIT_B to a ≤ 4.7 kΩ pull-up resistor to VCCO_0 to ensure clean Low-to-High transitions) .The device is ready for configuration after INIT_B goes High. 

4.If configuration has not completed properly, the status register provides important information about what errors might have caused the failure.

Check the status register values.

 

Thanks,

Priyanka

----------------------------------------------------------------------------------------------------

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3 Replies
Xilinx Employee
Xilinx Employee
513 Views
Registered: ‎06-13-2018

Re: Configure Kintex-7

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Hi @nawcadengineer2015 :

I believe you are using Free-Running CCLK method (by toggeling csi_b signal) for Non-continuous data loading.

selectMAPdata.PNG   

Few things I will suggest you to verify:

1. Confirm mode pins are set as M[2:0] = 110 for x32 Slave SlectMAP interface.

2. Make sure PROGRAM_B is connected to an external ≤ 4.7 kΩ pull-up resistor to VCCO_0 to ensure a stable High input, and it is recommended push-button to GND to enable manual configuration reset.

3. After the FPGA configuration is cleared (PROGRAM_B is pulsed Low), what is the status of INIT_B pin? This pin should be low when configuration is in reset state or when the FPGA is initializing (clearing) its configuration memory.  (Connect INIT_B to a ≤ 4.7 kΩ pull-up resistor to VCCO_0 to ensure clean Low-to-High transitions) .The device is ready for configuration after INIT_B goes High. 

4.If configuration has not completed properly, the status register provides important information about what errors might have caused the failure.

Check the status register values.

 

Thanks,

Priyanka

----------------------------------------------------------------------------------------------------

If you find any post has resolved your query, mark it as accepted solution.

Tags (1)
Participant nawcadengineer2015
Participant
461 Views
Registered: ‎02-27-2018

Re: Configure Kintex-7

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Thanks for your reply.  

I followed your instructions and verified everything is corrected.  When Program_B is reset, Init_B stay low for 1ms then go back up high.  After that I start to program but Done line is still low.  I don't know if the cclk speed is making a big difference.  I'm using axi clock which is 125mhz to drive cclk. I used JTAG to read the Register Status and you can see it below.  Based on the Register Status, is there a way you can check if there's data written into the FPGA or not? And how many data word left to configure FPGA etc? These extra info would be helpful to debug. 

 

REGISTER.CONFIG_STATUS.BIT00_CRC_ERROR 0
REGISTER.CONFIG_STATUS.BIT01_DECRYPTOR_ENABLE 0
REGISTER.CONFIG_STATUS.BIT02_PLL_LOCK_STATUS 1
REGISTER.CONFIG_STATUS.BIT03_DCI_MATCH_STATUS 1
REGISTER.CONFIG_STATUS.BIT04_END_OF_STARTUP_(EOS)_STATUS 0
REGISTER.CONFIG_STATUS.BIT05_GTS_CFG_B_STATUS 0
REGISTER.CONFIG_STATUS.BIT06_GWE_STATUS 0
REGISTER.CONFIG_STATUS.BIT07_GHIGH_STATUS 0
REGISTER.CONFIG_STATUS.BIT08_MODE_PIN_M[0] 0
REGISTER.CONFIG_STATUS.BIT09_MODE_PIN_M[1] 1
REGISTER.CONFIG_STATUS.BIT10_MODE_PIN_M[2] 1
REGISTER.CONFIG_STATUS.BIT11_INIT_B_INTERNAL_SIGNAL_STATUS 1
REGISTER.CONFIG_STATUS.BIT12_INIT_B_PIN 1
REGISTER.CONFIG_STATUS.BIT13_DONE_INTERNAL_SIGNAL_STATUS 0
REGISTER.CONFIG_STATUS.BIT14_DONE_PIN 0
REGISTER.CONFIG_STATUS.BIT15_IDCODE_ERROR 0
REGISTER.CONFIG_STATUS.BIT16_SECURITY_ERROR 0
REGISTER.CONFIG_STATUS.BIT17_SYSTEM_MONITOR_OVER-TEMP_ALARM_STATUS 0
REGISTER.CONFIG_STATUS.BIT18_CFG_STARTUP_STATE_MACHINE_PHASE 000
REGISTER.CONFIG_STATUS.BIT21_RESERVED 0000
REGISTER.CONFIG_STATUS.BIT25_CFG_BUS_WIDTH_DETECTION 01
REGISTER.CONFIG_STATUS.BIT27_HMAC_ERROR 0
REGISTER.CONFIG_STATUS.BIT28_PUDC_B_PIN 0
REGISTER.CONFIG_STATUS.BIT29_BAD_PACKET_ERROR 0
REGISTER.CONFIG_STATUS.BIT30_CFGBVS_PIN 1
REGISTER.CONFIG_STATUS.BIT31_RESERVED 0

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Participant nawcadengineer2015
Participant
448 Views
Registered: ‎02-27-2018

Re: Configure Kintex-7

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I got the issue resolved.  You have to BIT Swap the bitstream file before programming it.