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Visitor
Visitor
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Registered: ‎09-10-2020

Configure Spartan 6 after power up

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Hi,

I don't have a lot of experience in the FPGA field.

I'm currently working on a FPGA project with a Spartan 6. The system on wich the FPGA is used will be embedded and powered by a battery.

The problem is that when I will powered down the FPGA, I will lost the configuration. Reconfigure it with the computer each time I power up the FPGA is not practical.

Is there a better way to do it ? I will use it with a microcontroller.

Thank you in advance.

Regards,

Antoine

 

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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @antoiner ,

If you follow any configuration methods apart from JTAG, mentioned in Chapter 2 of UG380 , then there is no need for you to configure FPGA each time from your PC.

Regards,
Deepak D N
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Xilinx Employee
Xilinx Employee
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Registered: ‎06-06-2018

Hi @antoiner ,

If you follow any configuration methods apart from JTAG, mentioned in Chapter 2 of UG380 , then there is no need for you to configure FPGA each time from your PC.

Regards,
Deepak D N
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Visitor
Visitor
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Registered: ‎09-10-2020

Ok thank you for this document.

But my main problem is : do i need to reconfigure my FPGA each time i power it up ? Is there a way to avoid it ?

Antoine

 

 

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Registered: ‎07-23-2019

Most FPGA are RAM based, so the way they work is they have a flash configuration memory and hardware is set up to automatically fetch the configuration from there. It takes a number of ms.

If you really want to avoid that (I can't see why that is a problem) there are Flash-based FPGAs, mostly from Microsemi, but bear in mind your choices will be very limited and their performance is not as great.

Even more alternatives: do you really need to power off? You may be fine by just stopping all FPGA activity.

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Registered: ‎06-21-2017

To echo @archangel-lightworks , the Xilinx FPGAs are RAM based.  If you turn them off, they need to be configured at power on.  You can add a flash memory and configure them from flash.  You could use the micro to configure the FPGA, depending on how it is connected.  Bit-banging from the micro will be a little slower, but not horribly so for a small FPGA.