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Newbie pvarnai
Registered: ‎02-29-2016

Configuring SPI clock to idle high


I am trying to use the SPI0 component of a Zynq XC7Z010 to read data from a 12-bit rotary encoder which uses an SSI protocol. I have a small example project set up in Vivado which enables the SPI0 to use EMIO ports and sets the pins I want to use. I also have the xspips driver working and am able to receive data from the encoder.

The problem I am facing is that I could only set up a clock signal which is idle low, while the encoder expects an idle high clock. Due to this, the first bits received are unusable, and I had to do some bit-manipulation to get these bits from the repeated data (the encoder starts sending data again after a 12 bit transmission). 


With an oscilloscope I tested out that the sent out clock signal is always idle low, whether the ACTIVE_LOW option is set or not for the SPI, so I concluded that that option is only for how the Zynq interprets the clock signal. How can I have a clock signal that is high by default? Do I have to manually invert them in the Vivado generated VHDL wrapper, or is there a simpler solution?


Thanks for any help!


The data sheet for the encoder:

Measured clock signal for a 2 byte transfer when ACTIVE_LOW is enabled:


and when it is not enabled:


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