cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Adventurer
Adventurer
9,296 Views
Registered: ‎05-27-2011

Correct iMPACT configuration BUT incorrect SDK configuration

Jump to solution

Hi All.

 

So I have a custom PCB with a PROM and Spartan 6 LX45 in a JTAG chain.

 

I can configure the FPGA from iMPACT with no issues at all. Downloaded .bit file is perfectly opperational.

 

The design contains an EDK Microblaze project, hence we are using the SDK to write embedded C. When I previously used the Digilent Nexys3 board I could program the FPGA (FPGA fabric configuration .bit and SDK .elf), through the SDK and use the microblaze UART IPcore to pipe out the microblaze STDIO to the SDK terminal window.

 

However SDK reports (a rather vague error), that:

Failed to download the bit file

Failed to program device 2 with bitstream C:/Users/.../SDK/SDK_Workspace/XpsMBprjFlites_hw_platform_1/download.bit

Program FPGA failed

 

With such a vague error it is difficult to see where the issue is. I dont think it is the configuration file (.bit) as iMPACT can configure this no problem, with appropriate LEDs, expansion header signals and clocks all being activated. 

 

Could it be a program .elf issue with respect to the microblaze BRAMs? I should note that the .bit file is exactly the same between both software configuration flows, so it must be something related to either:

 - SDK programming settings 

 - linker scripts, .elf compile settings etc

 

Now the .elf is actually a working .c file that was developed as part of the XUP tutorials, in this case generic flashing of some LEDs and STDIO output via UART. This works as it runs correctly on the Digilent Nexys 3 with the same Microblaze EDK design. 

 

Any thoughts?

Thanks, Ed

  

0 Kudos
1 Solution

Accepted Solutions
Highlighted
Adventurer
Adventurer
18,013 Views
Registered: ‎05-27-2011

Solved:

 

First I checked the XMP console terminal, which showed a bit more detail in this case "Wrong Device", as the Digilent uses the LX16, it was clear the project had picked up the wrong .bit (irespective of a successful 'export to SDK').

 

The solution to this, was that despite ISE/EDK export to SDK with bitstream, the SDK locally names the .bit file to system.bit or download.bit. When creating a Hardware Platform Specification, you can correctly grab the EDKprj.xlm, however I needed to force it to pick up the correct .bit file, although the .bmm file was fine.

 

Once this was done, I re-created the BSP and re-compiled the .elf with this BSP and HPS files.

 

Doing this now allows the FPGA configuration to proceed, on-bench the .bit is clearly loaded correctly.

 

I hope this helps others. 

Ed

View solution in original post

0 Kudos
2 Replies
Highlighted
Adventurer
Adventurer
9,284 Views
Registered: ‎05-27-2011

Further notes:

 - .elf passes elfcheck with no issues and runs fine on Digilent Nexys 3

 - linker script is the same as the EDK project is the same as that which correctly runs on Digilent Nexys 3

 

 - Manual SDK JTAG settings of:

   - PROM XCF16P IDcode 0xF5058093 with JTAG IR Length = 16 bits

   - FPGA S5 LX45 IDcode 0x04008093 with JTAG IR Length = 6 bits (DS indicated 0xX4008093 but this auto completed to 0x0, but as the DS indicated the X was to 4 bits that can be ignored I set them here to 0)

This however also doesn't work, returning the same error as above.

 

Thanks.

Ed

 

0 Kudos
Highlighted
Adventurer
Adventurer
18,014 Views
Registered: ‎05-27-2011

Solved:

 

First I checked the XMP console terminal, which showed a bit more detail in this case "Wrong Device", as the Digilent uses the LX16, it was clear the project had picked up the wrong .bit (irespective of a successful 'export to SDK').

 

The solution to this, was that despite ISE/EDK export to SDK with bitstream, the SDK locally names the .bit file to system.bit or download.bit. When creating a Hardware Platform Specification, you can correctly grab the EDKprj.xlm, however I needed to force it to pick up the correct .bit file, although the .bmm file was fine.

 

Once this was done, I re-created the BSP and re-compiled the .elf with this BSP and HPS files.

 

Doing this now allows the FPGA configuration to proceed, on-bench the .bit is clearly loaded correctly.

 

I hope this helps others. 

Ed

View solution in original post

0 Kudos