Could I hot plug JTAG cable connected direct with FPGA

[greatmaverick]

My FPGA JTAG pins is diectedly connected with JTAG cable. Can I plug it when FPGA is powered on? Can I take it away when FPGA is powered on after downloading the bit stream?

[drjohnsmith]

yes

[greatmaverick]

Hi,drjohnsmith Could you please possibly tell me why. Thank you.

[drjohnsmith]

Sorry,

you ask can you , and then ask why ?

confused,

Why would you not be able to ?
What makes you ask the question ?
what problem are you trying to sort out ?

[markg@prosensing.com · Accepted solution]

@greatmaverick 

I say, you should not hot-plug nor hot-unplug the JTAG cable to/from the FPGA board.

Page 20 of DS593(v1.5.1) says:

No damage to Platform Cable USB II occurs if the A–B (USB) cable is unplugged from the host while the ribbon cable or flying leads are attached to a powered target system. Similarly, no damage to target systems occurs if Platform Cable USB II is powered and attached to the target system while the target system power is off.

Hmmm, the second sentence supports the "yes" answer of @drjohnsmith.  However, I don't think the DS593 comments fully answer your question.

At our workplace we try to always use the following procedure:

1. Attach the JTAG connector of the UNPOWERED programmer (eg. Platform Cable USB) to the UNPOWERED FPGA board.
2. Power up the FPGA board.
3. Plug the USB cable from the programmer into the PC
4. Use Vivado/iMPACT
5. Close Vivado/iMPACT
6. Unplug USB cable from the PC
7. Power down the FPGA board
8. Remove JTAG connector from the FPGA board

The JTAG ribbon cable connector on the Platform Cable USB does not have special hot-plug features(eg. GND pin connects first).  That is, suppose your Platform Cable USB is attached to the PC and the PC is sitting on some elevated voltage.  If you start plugging the JTAG connector onto the FPGA board and the GND pin isn't the first to connect then ZAP - you could damage the FPGA! 

Also, the Platform Cable USB gets partially powered from the JTAG pin, VREF.  So, as you slowly push on the JTAG connector, VREF and the JTAG digital lines will be making intermittent contact.  This intermittent contact of the connector pins could send a undesirable JTAG message to the powered-up FPGA.

Finally, AR#66954 warns of "intermittent configuration failures" caused by mishandling the JTAG connection.

So, be safe, and don't hot-plug that JTAG connector.

Cheers,
Mark

[barriet]

#include"thisisjustpersonalopinion.h"

I'm inclined to agree with Mark here.

The programming cable & FPGAs are often a non-trivial expense, particularly with the larger FPGAs. Let alone the time to try to narrow down if your hardware was damaged and then replace it - and the associated opportunity cost There's probably an appropriate seat-belt analogy in here somewhere.

Cheers,

bt

[drjohnsmith]

You just have to make certain you have a programable device on the board to program,
Not all systems I get to design do, they are designed to be programmed over say USB
, and for testing , we have to use JTAG , and we have to plug / unplug the programmer.

we do however, put proper ESD protection and buffering on the JTAG lines .
but that wasn't the question, which was can you , to which the answer is yes.