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Registered: ‎07-15-2020

Create IO constraint in partial reconfiguration design zynq FPGA

I am working on partial reconfiguration implementation and I want to map some signals through GPIO to push buttons and leds on the FPGA , How can I do that ,as I get error during bitstream generation , I defined in bitstream setting the Pre-setting the command to ignore the error message "set_property SEVERITY {Warning} [get_drc_checks UCIO-1]" and I still get the same error. 

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