I'm attempting to have a design that utilizes PR. I believe I'm supposed to use the AXI_HWICAP IP to enable PR during runtime. I've looked at these guides:
https://www.xilinx.com/support/documentation/ip_documentation/axi_hwicap/v3_0/pg134-axi-hwicap.pdf
This is a picture of my BD that I'm planning on have 5 PR configurations.
Does this look correct? When I attempt to implement, Vivado returns this error message: "[DRC UTLZ-1] Resource utilization: ICAPE2 over-utilized in Top Level Design (This design requires more ICAPE2 cells than are available in the target device. This design requires 5 of such cell types but only 2 compatible sites are available in the target device. Please analyze your synthesis results and constraints to ensure the design is mapped to Xilinx primitives as expected. If so, please consider targeting a larger device.)"