cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Observer
Observer
167 Views
Registered: ‎06-03-2019

Custom IP questions

Hello,

I created a custom AXI 4 IP but am having a bunch of difficulties trying to interface with it.  My VHDL code is attached (PW_Counter_Top.v) which is a pulse width calculator that I was able to successfully simulate.  

When modifying the AXI files I get this error that I can't seem to fix..

[Synth 8-6859] multi-driven net on pin Q with 1st driver pin 'U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_hi_reg[7]/Q' ["c:/Arty_Z7_FPGA_Projects/Xilinx_Training_labs/Lab_Downloads/genLoops/completed/KCU105/Final_PW/Final_PW.srcs/sources_1/bd/top_module/ipshared/5b80/src/PW_Counter_Top.vhd":75]

 

My other main question is, once this is fixed and assuming everything else if correct I would like to output the values of pulse_length_hi and pulse_length_lo out of the zynq uart.  How would I access these values in Vitis (SDK)?

 

I have also attached my custom IP files and C code to this in case that is of any help.

Thank you for any help

 

 

PWC_BlockDiagram.png
0 Kudos
9 Replies
Highlighted
Observer
Observer
164 Views
Registered: ‎06-03-2019

Forgot to add the c code.  

 

Here it is

Tags (1)
0 Kudos
Highlighted
Scholar
Scholar
146 Views
Registered: ‎05-21-2015

@ejleiss,

Why aren't you connecting either your clock or your reset to the pulse width counter?  You are also setting pulse_length_* twice--once from within the counter and once at the end of your user code in the *_S00_AXI.vhd file.  This should be an error.  Only one wire can ever drive another to avoid short circuits.

Dan

0 Kudos
Highlighted
Observer
Observer
141 Views
Registered: ‎06-03-2019

I did notice the clock and reset after I posted this... but I am confused that you say I'm setting the pulse_length twice.  I am setting it in the counter, but I thought I had to associate this with the IP registers which is why I did this in the user logic

pulse_length_hi <= slv_reg0(7 downto 0);
pulse_length_lo <= slv_reg1(7 downto 0);

Is this incorrect?

How else would it know where these values are stored?

Apologize for all the newbie questions.

Tags (1)
0 Kudos
Highlighted
Scholar
Scholar
134 Views
Registered: ‎05-21-2015

@ejleiss,

Try this: back up and tell me, how is this pulse width counter to work?  Are the results to be able to be *read* by the bus, or is a pulse width to be controlled by *writes* to the bus?  If the former, then you may wish to set slv_reg* with the pulse_length.  If the latter, then you'll want to send slv_reg* to your pulse width counter core.  In no case do you want to set the pulse length twice.

Dan

0 Kudos
Highlighted
Observer
Observer
114 Views
Registered: ‎06-03-2019

My thought is the pulse width counter outputs (pulse_length_hi and pulse_length_lo) need to be read from the bus... So thinking about it that way, I would need to set slv_reg0 and slv_reg1 to those values...

 

in the user logic I now have:

slv_reg0(7 downto 0) <= pulse_length_hi;

slv_reg1(7 downto 0) <= pulse_length_lo;

I had to change pulse_length_* to buffer so it could be written, but I will have to try this in the morning when I get back to my development board.

Thanks for your help

0 Kudos
Highlighted
Observer
Observer
111 Views
Registered: ‎06-03-2019

and when doing that, I get these errors when I try to generate bitstream

 

[DRC MDRV-1] Multiple Driver Nets: Net top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_hi[0] has multiple drivers: top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_hi_reg[0]/Q, and top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/slv_reg0_reg[0]/Q.

 

[DRC MDRV-1] Multiple Driver Nets: Net top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_hi[1] has multiple drivers: top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_hi_reg[1]/Q, and top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/slv_reg0_reg[1]/Q.

.

.

. etc........

[DRC MDRV-1] Multiple Driver Nets: Net top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_lo[7] has multiple drivers: top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/slv_reg1_reg[7]/Q, and top_module_i/myip_pwc_0/U0/myip_pwc_v1_0_S00_AXI_inst/U0/pulse_length_lo_reg[7]/Q.

0 Kudos
Highlighted
Scholar
Scholar
94 Views
Registered: ‎05-21-2015

@ejleiss,

That's because you are trying to drive slv_reg* from outside of its process.

A register can only be driven from within one process.  There's a process within your S00* file that drives slv_reg*.  Within the if block checking for the rising clock edge is where you need to set these values.  More than that, you need to set them at the bottom of the rising clock edge block but outside of any other if's.  If you try to set slv_reg* from anywhere else in that VHDL file, you'll get a multiple-driver conflict warning--like you should have been getting with the pulse_length* registers before.

Dan

Highlighted
Observer
Observer
86 Views
Registered: ‎06-03-2019

Thank you Dan.  You have incredible patients.  I will work on this and updatey results. 

0 Kudos
Highlighted
Observer
Observer
49 Views
Registered: ‎06-03-2019

by patients I meant patience obviously... 

I added  slv_reg0 <= pulse_length_hi;
              slv_reg1 <= pulse_length_lo;

after the final if statement of the slv_register write and the IP is now working.

I really appreciate your help.  This helped clarify things for me.

0 Kudos