10-09-2020 05:58 AM
We have designed custom board using xc7z020-clg484 taking reference from the Avnet Zed board. The custom board under went DDR3 Diagnostic test passed using the default values from the Vivado 2018.3 DDR configuration test window.
When we tested our other custom boards designed using XC7Z030/45-FBG/FFG with calculated values of package delay and actual board length values, the DDR diagnostic test is being failed.
We are testing PS side DDR.
We are using MT41K256M16HA-125 from Micron.
We followed this procedure for calculating values for the DDR configuration:-
I need clarifications on the following:-
1.Is there any difference in testing if the FPGA package changes?
2.is there any difference design constraints while doing for different packages?
3.Are there any complete user manual for the DDR diagnostic test.
10-09-2020 06:34 AM