08-06-2020 11:02 AM
What is the best way to delay an incoming signal so as to have a lot of very repetitive (ideally always equal) delay through a great number of stages? And this delayed signal should be able to be latched by e.g. flip-flops along the delay line. Like in various TDC schemes, for instance.
08-06-2020 11:19 AM
Do you want to delay by an integer number of clocks? Then this technique might work for you. A fractional number of clocks? Then look up the IDELAYE2 primitive. A fractional number of clocks? Then you might need to do some form of sub-sample interpolation.
08-06-2020 01:18 PM
It is a fractional number of clocks or even a smaller delay.
I'll look up the IDELAYE2 primitive indeed, thanks.
How do you perform a sub-sample interpolation?
08-06-2020 01:34 PM