07-26-2020 06:44 AM
Hi, I'm designing a digital circuit for my measurement on FPGA.
Reading user guide regarding with I/O standard, I found that there are two classes for HSTL and SSTL.
What is the difference between class 1 and class 2 ?
I know that only HR bank supports class2.
But I wanna know what is difference between HSTL_1 and HSTL_2 from a circuit perspective.
Thank you.
07-26-2020 04:39 PM
According to standard JESD8-6, there are actually four classes (I -thru- IV) of the HSTL standard with the difference being output drive (current) requirements. You can see this in Table 9 of DS182(v2.18), which shows IOL=IOH=8mA for HSTL-I and IOL=IOH=16mA for HSTL-II.
Also, in UG471(v1.10), Fig 1-46 shows that HSTL-I is terminated at only the far-end. Fig 1-49 in UG471 shows that HSTL-II is terminated at both the near-end and far-end.
Cheers,
Mark
07-26-2020 04:39 PM
According to standard JESD8-6, there are actually four classes (I -thru- IV) of the HSTL standard with the difference being output drive (current) requirements. You can see this in Table 9 of DS182(v2.18), which shows IOL=IOH=8mA for HSTL-I and IOL=IOH=16mA for HSTL-II.
Also, in UG471(v1.10), Fig 1-46 shows that HSTL-I is terminated at only the far-end. Fig 1-49 in UG471 shows that HSTL-II is terminated at both the near-end and far-end.
Cheers,
Mark
07-26-2020 06:58 PM
Clear.
Thank you very much !