cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
betontalpfa
Explorer
Explorer
875 Views
Registered: ‎10-12-2018

Digilent programming-cable - Done pin is not high

Jump to solution

Hi,

We have problem programming FPGAs using Digilent programming-cable. Some of our (custom) board can be programmed, some cannot, but all of them can be programmed with standard Xilinx Blaster.

The following error comes up (in some cases with the Digilent cables), at the end of the programming: Done pin is not high.

So: The Digilent cable does works in some cases (with some boards) and all of our boards can be programmed in a way (with Xilinx Blaster). What can be the root-cause the programming problem of the Digilent cable and the boards?

We have reduced the JTAG clock frequency, but we see the same error.

Benedek

0 Kudos
1 Solution

Accepted Solutions
betontalpfa
Explorer
Explorer
706 Views
Registered: ‎10-12-2018

Hi,

We have inserted a schmitt trigger clock buffer, in the TCK clock line. Now, everithing is fine.

Benedek

View solution in original post

6 Replies
u4223374
Advisor
Advisor
863 Views
Registered: ‎04-26-2015

Which FPGAs?

 

The HS3 isn't compatible with some of the really old ones, but any reasonably modern FPGA should work.

 

Might be worth posting this on Digilent's forums, since it seems to be an issue with a Digilent product.

0 Kudos
drjohnsmith
Teacher
Teacher
857 Views
Registered: ‎07-09-2009

good first startt lowering the JTAG speed,

Its unclear are these boards all the same design, and some can be programed with HS3 and some cant, 

   or are they different board designs ? 

    

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
betontalpfa
Explorer
Explorer
842 Views
Registered: ‎10-12-2018

Hi,

The FPGA Device is Zynq-7000, xc7z030sbg485-2.

The boards are different pieces (S/N) of the same product.

Benedek

0 Kudos
drjohnsmith
Teacher
Teacher
826 Views
Registered: ‎07-09-2009
So if some can be programmed, its not incompatibility.
Out with the scope,
check the JTAG chain,
Im wondering if some of the boards have faults,



<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos
betontalpfa
Explorer
Explorer
707 Views
Registered: ‎10-12-2018

Hi,

We have inserted a schmitt trigger clock buffer, in the TCK clock line. Now, everithing is fine.

Benedek

View solution in original post

drjohnsmith
Teacher
Teacher
701 Views
Registered: ‎07-09-2009
looks like you had signal integrity problems,
its normal to put terminator and / buffering on the JTAG lines,

https://www.xjtag.com/about-jtag/design-for-test-guidelines/
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
0 Kudos