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Explorer
Explorer
8,088 Views
Registered: ‎09-02-2009

Does JTAG work under BPI mode

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Hi experts,

 

I found a strange description in page54 of UG470, I copied it below. If the mode pins are set 010 (BPI), can it work during debugging with JTAG. What does it mean, should add a DIP switch or not? We don't do it in Virtex5, Virtex4 and Spartan3.

 

 

10. The FPGA mode (M[2:0]) pins are shown set to Master BPI mode (010). The implementation of a board-level option that enables the user to change the FPGA mode pins to JTAG mode (101) is recommended to enable JTAG-based debug
capability for the FPGA during design. This is not required, but the JTAG mode setting ensures that there is no interference from the Master BPI configuration during debug.

 

Thanks.

Chris.

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Community Manager
Community Manager
14,205 Views
Registered: ‎07-23-2012
Hi Chris,

Even when the mode pins are set for BPI mode, you can still access the FPGA through JTAG.

The JTAG mode has highest priority over all the configuration modes. In other words, irrespective of the mode pin settings, you can program/access/ debug fpga through JTAG.

Regards,
Krishna
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Community Manager
Community Manager
14,206 Views
Registered: ‎07-23-2012
Hi Chris,

Even when the mode pins are set for BPI mode, you can still access the FPGA through JTAG.

The JTAG mode has highest priority over all the configuration modes. In other words, irrespective of the mode pin settings, you can program/access/ debug fpga through JTAG.

Regards,
Krishna
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Explorer
Explorer
8,062 Views
Registered: ‎09-02-2009

Hi Krishna,

 

Thanks for your comments. It's a good news for me, I thought I had to add a DIP switch.

 

I'm just curious why xilinx added such a confusing note.

 

Thanks.

Chris. 

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Xilinx Employee
Xilinx Employee
8,041 Views
Registered: ‎10-11-2007

I think this is a carry over from the previous architecture when there was a potential contention in some rare case. The 7-series user guide should not have this remark and will be removed.

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