02-07-2020 08:57 AM
i'm quite new to partial reconfiguration and i have some issues/questions that i can't overcome all by myself.
I'll try to summarize what i want to do and what i've done so far in order to let you understand where the problems are.
What i want to do:
I want to split my design into two parts, the static part and the dynamic part. The dynamic part must be a custom IP core that does nothing more than perform a simple operation on two 32 bit-wide inputs and give back the result as its output.
I've created two custom ip cores, the first one does a bitwise "and" while the second one does a bitwise "xor". Both are AXI4 LITE slave ip cores.
In order to connect these ipcores to my block design i've thought to instantiate a PR controller and a PR decoupler and create an AXI4 LITE master interface in the PR decoupler and make it external.
In order to enable partial reconfiguration of my ip core, i've created and HDL top module that has two components: the block diagram wrapper and the custom ip itself.
Obviously in the top module I've connected the master interface of the PR decoupler to the slave interface of the custom IP.
I can synthetize, my design, successfully and even assign a Pblock to my custom IP. Implementation and bitstream generation are done without any particular problem.
I program my fpga by using "open hardware" option in vivado where i can flash both bitstreams.
What i want to do:
I want to test my design by writing a simple driver in C for my custom IP. Basically i'd like to access my ip's base address and write its registers as if it was a component of my block design. The problem is i can't do that because I've no base address at all. The base address of the PR decoupler AXI4 lite Master interface is not shown in the address editor since its pins are unconnected.
I've tried even to add an AXI4 lite master port to the axi periph and make it external (deleting the one belonging to the PR decoupler) and connecting it to my ip in the top level entity, but even if i manage to get the interface base address in the driver i cannot trigger the execution of my ip core.
Here's my driver (launched from Vitis IDE)
u32 input_a = 0x00000001;
u32 input_b = 0x00000003;
output = Xil_In32(XPAR_M02_AXI_0_BASEADDR+2);
I hope somebody can help me to sort this out.
Screenshot of my designs are attached to this thread.
Thanks in advance.
02-19-2020 11:27 AM