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ali_flt
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Registered: ‎08-10-2020

Dynamic Function exChange: How to have AXI Bus as physical interface points between static and reconfigurable logic?

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Hi,
I'm currently trying to setup a partially reconfigurable system using the UG947 Lab 2 on ZCU104 board.
But the interface points between my reconfigurable modules and the static parts are AXI Buses.
As you know, by changing the RM design, the width of some signals inside a AXI Bus (like address width) may change automatically but the physical interfaces between the RM and the static part of the logic must stay unchanged for all RMs in the reconfigurable partitions. 
So I wanted to know if there is a workaround for this issue because it is very natural to need AXI buses for interconnection between modules.

Thanks,
Ali 

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ali_flt
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Contributor
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Registered: ‎08-10-2020

I found the solution to my issue by using the DFX AXI shutdown manager IP. I guess I had to search more.
But now there is another issue which is described here. I can't understand why xilinx wouldn't fix such an obvious bug. Why should there be std_logic_vector(0 to 0) signals?  
This is very problematic when you're working with Reconfigurable modules.

View solution in original post

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ali_flt
Contributor
Contributor
154 Views
Registered: ‎08-10-2020

I found the solution to my issue by using the DFX AXI shutdown manager IP. I guess I had to search more.
But now there is another issue which is described here. I can't understand why xilinx wouldn't fix such an obvious bug. Why should there be std_logic_vector(0 to 0) signals?  
This is very problematic when you're working with Reconfigurable modules.

View solution in original post

0 Kudos