I'm trying to implement the DPR flow on the ZCU104 board. I have developed the Vivado project and a Vitis application. In this latter I use the "xilfpga" library following the configuration flow suggested in the ug1085-zynq-ultrascale-trm (Ch.11) document. In particular to produce a partial reconfiguration I have to implement the following steps:
//Initialize PCAP Interface
Status = XFpga_PcapInit (XFPGA_PARTIAL_EN);
//Write a Bitstream Through the PCAP
Status = XFpga_WriteToPcap (PARTIAL_ADDER_BITFILE_LEN,(UINTPTR)PARTIAL_ADDER_ADDR);
//Wait for the PL Done Status
Status = XFpga_PLWaitForDone();
Unfortunately the XFpga_PLWaitForDone() function returns the XFPGA_ERROR_PCAP_PL_DONE error.
Does anyone have some suggestions to solve my problem?