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Explorer
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Registered: ‎09-14-2018

EMCCLK pin and must be programmed as an input when the ExtMasterCclk_en option is not set to Disable

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Hello,

KCU105 Ultrascale evaluation board, Vivado 2018.3.

I created the simplified KCU105 IPI example design and successfully generated the image. Then I added several custom IPs to that design. The bitstream generation failed.  Here is the message:  

  • Write Bitstream
  • [Designutils 12-2331] Pin IOB_X1Y101 is the EMCCLK pin and must be programmed as an input when the ExtMasterCclk_en option is not set to Disable.
  • [Common 17-69] Command failed: Bitgen failed.

I do not understand why Vivado behaves differently. Here are the EMCCLK related lines in .xdc file:

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]

set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EMCCLK_IBUF]

set_property PACKAGE_PIN K20 [get_ports EMCCLK]

set_property IOSTANDARD LVCMOS18 [get_ports EMCCLK]

EMCCLK is described as input in the top-level design file. There is no intention to use EMCCLK. What should be done to make Vivado happy?   

  Thank you.

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Registered: ‎01-22-2015

@arotenst 

If your EMCCLK is LVCMOS18 compatible and VCCO_65=VCCO_0=1.8V then use only the following constraints in your Vivado project xdc file.

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]

– and do not use the CLOCK_DEDICATED_ROUTE,  PACKAGE_PIN, and IOSTANDARD constraints for EMCCLK.

– and check physical connection of the CFGBVS pin on your FPGA (see Table 1-11 in UG570 (v1.12))   << IMPORTANT FOR AVOIDING FPGA DAMAGE

Cheers,
Mark

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Registered: ‎01-22-2015

@arotenst 

If your EMCCLK is LVCMOS18 compatible and VCCO_65=VCCO_0=1.8V then use only the following constraints in your Vivado project xdc file.

set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]

– and do not use the CLOCK_DEDICATED_ROUTE,  PACKAGE_PIN, and IOSTANDARD constraints for EMCCLK.

– and check physical connection of the CFGBVS pin on your FPGA (see Table 1-11 in UG570 (v1.12))   << IMPORTANT FOR AVOIDING FPGA DAMAGE

Cheers,
Mark

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Registered: ‎09-14-2018

Thank you, Mark.

I will try it. The strange thing was that the same constraint file works for one project and did not for another, a similar one.

Thanks again.   

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Registered: ‎01-22-2015

-another thought:

With the CLOCK_DEDICATED_ROUTE and PACKAGE_PIN constraints that you showed, it looks like you were trying to bring the EMCCLK into the FPGA fabric. 

The FPGA pin for EMCCLK is usually a multipurpose pin.  You can use it for logic IO/clocks -or- you can use it for the EMCCLK, but you can't use it for both (I think).  That is, the EMCCLK cannot be routed directly from this pin into the FPGA fabric.

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Registered: ‎09-14-2018

Thank you, Mark.

Actually, I did not have intention to use EMCCLK  in any way.

I mistakenly had a line: set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets EMCCLK_IBUF], as it was in example. Commenting that line as well as PACKAGE_PIN  helped.

Thank you.

 

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