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Registered: ‎11-12-2018

ERROR: [Place 30-154] Unroutable Placement! A MMCM can only drive loads in the same clock region. The following MMCM clock loads are placed too far from the MMCM to be routable. plle2

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Hi, 

I am getting the following error. 

ERROR: [Place 30-154] Unroutable Placement! A MMCM can only drive loads in the same clock region. The following MMCM clock loads are placed too far from the MMCM to be routable.

                plle2_adv_inst2 (PLLE2_ADV.CLKOUT0) is provisionally placed by clockplacer on PLLE2_ADV_X1Y4 (in SLR 1)

                The loads are distributed to 1 user pblock constraints. In addition, there are 20 loads not in user pblock constraints.

                Displaying only the first 20 or fewer instances under each constraint as list of loads is too long

                Displaying first 20 loads not in user pblock constraint:

                IDDR_rx1_inst24 (IDDR.C) is locked to ILOGIC_X1Y203 (in SLR 1)

                IDDR_rx1_inst34 (IDDR.C) is locked to ILOGIC_X1Y239 (in SLR 1)

                IDDR_rx1_inst2 (IDDR.C) is locked to ILOGIC_X1Y257 (in SLR 1)

My Design has a clock input clk20 which runs at 50Mhz and has to drive IDDR instances (total 40 such instances) i.e., data is 80 bit sitting in 3 clock regions. What is the ideal clock network I need to use in the design to sample these IDDR instances?

I tried the below configurations:

i/p PAD -> MMCM -> IDDR instance (didn't work. Got the above error)

i/p PAD -> MMCM -> BUFR -> IDDR instances (didn't work. )

i/p PAD -> MMCM -> BUFMR -> IDDR instances (didn't work. I read that BUFMR can drive only BUFR/I or BUFIO/I or PHASE_IN,..... )

Can you please suggest me?

I used earlier i/p PAD -> BUFG -> IDDR instances. But this approach eats some path delay ~2 ns to reach clk from i/p PAD to IDDR instance. (This approach worked but looks the routing path is long.

Thanks,

-Suresh

 

 

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Registered: ‎01-22-2015

Suresh,

You are welcome.  

Instead of using three BUFR in parallel, you can also use three BUFIO in parallel for IDDR clocking.  The BUFIO approach should give you less clock delay than the BUFR approach.

Mark

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Registered: ‎01-22-2015

@gsuresh418 

It sounds like you are using a 7-Series FPGA.  If so, then your go-to reference for clocking is Table 1-1 in UG472.   If your IDDRs are located in three vertically adjacent clocking regions, then you can use BUFMR>BUFRs to drive them all.  Otherwise, the only thing that can drive “Any clocking point in the fabric and I/O” is the BUFG.  So, here are two options for you:

PAD > IBUF > BUFG > IDDR
PAD > IBUF > MMCM > BUFG > IDDR

In 7-Series FPGAs, all the BUFG are located in the center of the die.  So, the routes from PAD>IBUF>BUFG will look long, but there is nothing you can do to shorten them.

Cheers,
Mark

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Registered: ‎11-12-2018

Hi,

BUFG is working for me.

What if I want to use BUFMR -> BUFR approach. Do I need to use three BUFR in parallel to drive the IDDR instances sitting in 3 clock regions as shown in the attached file?

 

 

 

BUFMR.png
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Updated diagram

BUFMR.png
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Registered: ‎01-22-2015

@gsuresh418 

Yes, your diagram shows correctly how to use BUFMR and BUFR.  For more information on using BUFMR and BUFR, see Appendix A in UG472.

Mark

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Thanks Mark,

Regards,

-Suresh

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Registered: ‎01-22-2015

Suresh,

You are welcome.  

Instead of using three BUFR in parallel, you can also use three BUFIO in parallel for IDDR clocking.  The BUFIO approach should give you less clock delay than the BUFR approach.

Mark

View solution in original post

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Okay. Thanks,

-Suresh

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