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Visitor arauch
Visitor
1,217 Views
Registered: ‎10-05-2018

Error: [Labtools 27-3165] End of startup status: LOW

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Hi, 

 

I am trying to program an Artix-7 FPGA (XC7A50T-2LE) in Vivaado 2017.4, but receive the error [Labtools 27-3165] End of startup status: LOW.

 

I am able to communicate with the chip to read the configuration registers and have tried adjusting the JTAG clock speed. I've monitored the chip voltages and there is no dip in chip voltage during programming. The PUDC_B pin is set so all unconnected IOs are pulled high. During programming the INIT_B line pulses low, but PROGRAM_B does not.  

 

Attached is a screenshot of the configuration status registers. 

 

Any help in fixing is appreciated, 

Andrew

config_bits.PNG
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Visitor arauch
Visitor
1,159 Views
Registered: ‎10-05-2018

Re: Error: [Labtools 27-3165] End of startup status: LOW

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I was able to successfully configure the FPGA once I had programmed the PIC also on the board. The unprogrammed PIC must have been pulling the DONE bit low, preventing successful configuration. 

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Xilinx Employee
Xilinx Employee
1,185 Views
Registered: ‎03-07-2018

Re: Error: [Labtools 27-3165] End of startup status: LOW

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Hi @arauch

 

What is minimum frequency you tried to configure FPGA with Vivado? (Try with 3Mhz)

What do you mean by "During programming the INIT_B line pulses low, but PROGRAM_B does not" ? Check your program_b circuit.

Is it custom board or Xilinx Board?

As your mode pins are set to M[2:0] = 101 it's JTAG only mode. You can configure FPGA through JTAG only in this mode.

If you are trying to configure using flash then you need to change mode pins. Check UG470 (v1.13.1) for more details.

 

Regards,

Bhushan

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Regards,
Bhushan

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Visitor arauch
Visitor
1,176 Views
Registered: ‎10-05-2018

Re: Error: [Labtools 27-3165] End of startup status: LOW

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I have tried all the speed options including 3 MHz and going down to 750 kHz. 

 

This is a custom board that I am trying to configure via JTAG. Do I need to pulse PROGRAM_B low externally in this mode? That line is pulled high through a 4.64K resistor, but I thought the FPGA would pulse it low like the INIT_B line during JTAG configuration. 

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Visitor arauch
Visitor
1,160 Views
Registered: ‎10-05-2018

Re: Error: [Labtools 27-3165] End of startup status: LOW

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I was able to successfully configure the FPGA once I had programmed the PIC also on the board. The unprogrammed PIC must have been pulling the DONE bit low, preventing successful configuration. 

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Contributor
Contributor
957 Views
Registered: ‎11-20-2018

Re: Error: [Labtools 27-3165] End of startup status: LOW

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