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Registered: ‎08-20-2019

Estimated Reconfiguration time Spartan7 or Artix7 fpga

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Hello, I do not manage to figure out the estimated reconfiguration time for Spartan-7 XC7S25 (or Artix-7 XC7A25T) FPGA.

How can I do an estimation? I know that I can do it dividing the bitstream size per clock frequency*bus width .

I think that the bitstream size is 1620 kbits, whereas I cannot find the clock frequency and the bus width.

Thanks

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Registered: ‎01-22-2015

Re: Estimated Reconfiguration time Spartan7 or Artix7 fpga

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@matteo.bertolino92 

Welcome to the Xilinx Forum!

    I know that I can do it dividing the bitstream size per clock frequency*bus width

Roughly, you are correct !

The bitstream size for the Spartan-7 and Artix-7 FPGAs can be found in Table 1-1 of UG470.

The configuration clock can be generated by the FPGA itself and is called CCLK.  Vivado tools allow you to set the CCLK frequency to values between 3-66MHz (see chapter 2 in UG470 and Table A-1 in UG908).  For some methods of FPGA configuration, you can supply the configuration clock via the EMCCLK pin to the FPGA.  EMCCLK frequency can be higher than CCLK frequency – again see UG470, chapter 2.

Finally, bus-width depends on the interface between the FPGA and the device (typically a Flash memory IC) that holds the bitstream.  Often the bus-width is 1 (called SPIx1) or 4 (called SPIx4).  Again, see UG470 for bus-width options.

Mark

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Registered: ‎01-22-2015

Re: Estimated Reconfiguration time Spartan7 or Artix7 fpga

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@matteo.bertolino92 

Welcome to the Xilinx Forum!

    I know that I can do it dividing the bitstream size per clock frequency*bus width

Roughly, you are correct !

The bitstream size for the Spartan-7 and Artix-7 FPGAs can be found in Table 1-1 of UG470.

The configuration clock can be generated by the FPGA itself and is called CCLK.  Vivado tools allow you to set the CCLK frequency to values between 3-66MHz (see chapter 2 in UG470 and Table A-1 in UG908).  For some methods of FPGA configuration, you can supply the configuration clock via the EMCCLK pin to the FPGA.  EMCCLK frequency can be higher than CCLK frequency – again see UG470, chapter 2.

Finally, bus-width depends on the interface between the FPGA and the device (typically a Flash memory IC) that holds the bitstream.  Often the bus-width is 1 (called SPIx1) or 4 (called SPIx4).  Again, see UG470 for bus-width options.

Mark

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Registered: ‎08-20-2019

Re: Estimated Reconfiguration time Spartan7 or Artix7 fpga

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Dear Mark,

you did perfectly explained my the concepts I needed and how to find them. Thanks!

It was a bit difficult finding the right information at the beginning.

Matteo

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Registered: ‎07-09-2009

Re: Estimated Reconfiguration time Spartan7 or Artix7 fpga

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You might want to give mark some Kdos and close the case then.

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>