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Visitor enamdar
Visitor
858 Views
Registered: ‎05-07-2018

Exchange mcs file while running fpga!

Hi,

 

I need  a help about multiboot.

I have xc7a50tftg256-2 (artix-7) board. I want to multiboot process, I mean, I want to switch between mcs files while running fpga.  Can the process be done with 4 different mcs files, how can it be done?? and  Do I need use ICAPE2 primitive?

Note: I give a trigger on DSP , no external trig for switching.

 

Thanks, 

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5 Replies
Xilinx Employee
Xilinx Employee
824 Views
Registered: ‎11-30-2007

Re: Exchange mcs file while running fpga!

You will want to use the ICAPE2 primitive to initiate an IPROG command for MultiBoot configuration in 7 Series FPGAs.  You can reference Table 7-1: Example Bitstream for IPROG through ICAPE2 in the 7 Series FPGAs Configuration User Guide (UG470; v1.13) for the ICAP sequence.

 

fp_2_1.png

 

You will define the Warm Boot Start Address (WBSTAR Register) for the desired address in configuration memory you wish to jump in order to configure the FPGA with a new image.  You can reference Table 5-34: WBSTAR Register.

 

fp_2_2.png

 

You will want to create a state machine (or MicroBlaze with axi_hwicap IP) to issue an IPROG command.  You will need to consider the bit order and byte-swapping to properly create the state machine.  Below is a simple example of an FSM which will either IPROG to 0x00000000 or 0x00010000.  In this case, you would have to manually set the WBSTAR value but it gives you an idea.  In order to initiate the IPROG state machine, you would drive "mbt" high for one clock cycle.

 

Please note this VHDL is provided as an example and has not been tested.  The VHDL is provided "AS IS" without warranty of any kind, express or implied.

 

 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VComponents.all;

entity s7_mbt_fsm1 is
port (
  clk      : in  std_logic;
  mbt      : in  std_logic);
end s7_mbt_fsm1;

architecture rtl of s7_mbt_fsm1 is

  -- Signal Declarations
  signal icap_din  : std_logic_vector(31 downto 0);
  signal icap_dout : std_logic_vector(31 downto 0);
  signal icap_ce   : std_logic;
  signal icap_wr   : std_logic;

  -- State Machine Declarations
  type state_type is (IDLE, DUMMY1, DUMMY2, SYNC, NOOP1, WBST, ADDR, CMD, IPROG, NOOP2); 
  signal state, next_state : state_type; 

begin

  --#############################################--
  -- State Machine for ICAPE2 MultiBoot sequence --
  --#############################################--
  ICAPE2_0 : ICAPE2
  generic map (
    DEVICE_ID         => X"3636093", -- Specifies the pre-programmed Device ID value to be used for simulation purposes.
    ICAP_WIDTH        => "X32",      -- Specifies the input and output data width.
    SIM_CFG_FILE_NAME => "NONE"      -- Specifies the Raw Bitstream (RBT) file to be parsed by the simulation model.
  )
  port map (
    O     => icap_dout, -- 32-bit output: Configuration data output bus
    CLK   => clk,       -- 1-bit input: Clock Input
    CSIB  => icap_ce,   -- 1-bit input: Active-Low ICAP Enable
    I     => icap_din,  -- 32-bit input: Configuration data input bus
    RDWRB => icap_wr    -- 1-bit input: Read/Write Select input
  );

  --#############################################--
  -- State Machine for ICAPE2 MultiBoot sequence --
  --#############################################--
  process (clk)
  begin

    if rising_edge(clk) then

      case state is

        when IDLE =>
          if (mbt='1') then
            state     <= DUMMY1;
            icap_ce   <= '0';
            icap_wr   <= '0';
            icap_din  <= X"FFFFFFFF"; -- Bit Reversal of X"FFFFFFFF"
          else
            state     <= IDLE;
            icap_ce   <= '1';
            icap_wr   <= '1';
            icap_din  <= X"FFFFFFFF"; -- Bit Reversal of X"FFFFFFFF"
          end if;

        when DUMMY1 =>
          state     <= DUMMY2;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"FFFFFFFF";   -- Bit Reversal of X"FFFFFFFF"

        when DUMMY2 =>
          state     <= SYNC;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"5599AA66";   -- Bit Reversal of X"AA995566"

        when SYNC =>
          state     <= NOOP1;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"04000000";   -- Bit Reversal of X"20000000"

        when NOOP1 =>
          state     <= WBST;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"0C400080";   -- Bit Reversal of X"30020001"

        when WBST =>
          state     <= ADDR;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"00800000";   -- Bit Reversal of X"00010000" (MB1) & X"00000000" (MB2)

        when ADDR =>
          state     <= CMD;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"0C000180";   -- Bit Reversal of X"30008001"

        when CMD =>
          state     <= IPROG;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"000000F0";   -- Bit Reversal of X"0000000F"

        when IPROG =>
          state     <= NOOP2;
          icap_ce   <= '0';
          icap_wr   <= '0';
          icap_din  <= X"04000000";   -- Bit Reversal of X"20000000"

        when NOOP2 =>
          state     <= IDLE;
          icap_ce   <= '1';
          icap_wr   <= '1';
          icap_din  <= X"FFFFFFFF";   -- Bit Reversal of X"FFFFFFFF"

        when others =>
          state     <= IDLE;
          icap_ce   <= '1';
          icap_wr   <= '1';
          icap_din  <= X"FFFFFFFF";   -- Bit Reversal of X"FFFFFFFF"

      end case;
    end if;
  end process;

end rtl;

 

You will want to comply with the Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS181; v1.25) maximum ICAPE2 clock frequency.

 

fp_2_3.png

 

 

I hope this helps.

Tags (1)
Visitor enamdar
Visitor
816 Views
Registered: ‎05-07-2018

Re: Exchange mcs file while running fpga!

Thanks a lot for this answer. But I want to ask a question.

 

Which code/codes ICAPE2 primitive work on? (golden,update_1, update_2,update_3)

However, I want to switch other mcs file when every trigger(if mbt='1' then) so, ICAPE2 input address should be changed every time, right?

 

thanks.

 

 

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Xilinx Employee
Xilinx Employee
781 Views
Registered: ‎06-02-2017

Re: Exchange mcs file while running fpga!

Hi enamdar,

 

ICAP primitive is provideing post-configuration access to the configuration functions of the FPGA
by users.  That means user can use ICAP to send command and data to the FPGA configuration logic.

So when you want to switch mcs , you need to send all mcs which need to be switched into FPGA by ICAP in your logic design. The code Miker provided is a reference  how to instantie ICAP and how to use it to send command and data.

For more details, pls check the UG470.

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Visitor enamdar
Visitor
694 Views
Registered: ‎05-07-2018

Re: Exchange mcs file while running fpga!

Hi all,

I want to ask a question again about multiboot. I want to explain my situation clearly.

I have 3 vivado projects, bit streams and mcs files (golden,multiboot 1,multiboot 2). I put ICAPE2 primitive in golden project. Multiboot 1 and 2 projects have not ICAPE2 primitive. When power up, I observed output of multiboot1 project  in ILA. Now, I want to trig with serial channel and observed output of multiboot 2 project in ILA. Is this possible? Now, I trigged but no change in ILA, I still get output of multiboot1 project. How can I change this? what do I have to do in this case? can you help me please?

 

Thanks.

 

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Visitor enamdar
Visitor
690 Views
Registered: ‎05-07-2018

Re: Exchange mcs file while running fpga!

***correction : I have 3 vivado projects and bit files but one mcs file.

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