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Visitor
Visitor
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Registered: ‎06-13-2018

FPGA configuration time takes very long after PROG_B or Power recycle(Off and then On). Microblaze application configuration using SREC SPI Bootloader

I implemented the FPGA configuration method using Microblaze-AXI QSPI-STARTUPE3 primitive in XCKU060 FPGA.

SREC SPI Bootloader Application was created and Helloworld Application was created in XSDK.

The bit file created in the Vivado and the Bootloader elf are written to Flash(MT25QU256), and the Helloworld Application elf(offset 0x01800000) is written.

When PROG_B is pressed or Board Power is turned off and then on, the terminal window outputs as shown below to launch Hello world. FPGA configuration time takes within about 2 seconds. CONFIGRATE is set to 33MHz and BUS WIDTH is set to x4.

SREC SPI Bootloader
Loading SREC image from flash @ address: 01800000

Executing program starting at address: 00000000
Hello World

However, when PROG_B is pressed again on the board, or when Power is turned off and on, the FPGA Configuration takes about 85 seconds.

FPGA configuration failed first trial and then was done at next trial according to probing Flash interface signals.

MOSI did not output 0x6C command at First trial, MOSI did output 0x6C command at Next trial(After about 85 seconds). 

Is there any way to correct this?

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Visitor
Visitor
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Registered: ‎06-13-2018

Results of report_property -all [current_design] are below;

 

BITSTREAM.CONFIG.CONFIGRATE enum false 33
BITSTREAM.CONFIG.SPI_32BIT_ADDR enum false YES
BITSTREAM.CONFIG.SPI_BUSWIDTH enum false 4
BITSTREAM.CONFIG.SPI_FALL_EDGE enum false YES
BITSTREAM.GENERAL.COMPRESS enum false TRUE
CFGBVS enum false GND
CLASS string true design
CONFIG_MODE enum false SPIx4
CONFIG_VOLTAGE enum false 1.8
CONSTRSET fileset true constrs_1

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