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pavel_47
Voyager
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Registered: ‎05-30-2018

FRAME_ECC testing on ZC706

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Here is a very simple testing of FRAME_ECC.

It allows to control SyndromeValid signal ... just to see that Readback CRC is running:

module top(
    output SyndromeValid
    );
    
    FRAME_ECCE2 #(
          .FARSRC("FAR"),                // Determines if the output of FAR[25:0] configuration register points to
                                          // the FAR or EFAR. Sets configuration option register bit CTL0[7].
          .FRAME_RBT_IN_FILENAME("NONE")  // This file is output by the ICAP_E2 model and it contains Frame Data
                                          // information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
                                          // will parse this file, calculate ECC and output any error conditions.
       )
       FRAME_ECCE2_inst (
          .CRCERROR(),             // 1-bit output: Output indicating a CRC error.
          .ECCERROR(),             // 1-bit output: Output indicating an ECC error.
          .ECCERRORSINGLE(), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
          .FAR(),                       // 26-bit output: Frame Address Register Value output.
          .SYNBIT(),                 // 5-bit output: Output bit address of error.
          .SYNDROME(),             // 13-bit output: Output location of erroneous bit.
          .SYNDROMEVALID(SyndromeValid),   // 1-bit output: Frame ECC output indicating the SYNDROME output is
                                           // valid.
    
          .SYNWORD()                // 7-bit output: Word output in the frame where an ECC error has been
                                           // detected.
    
       );
endmodule

Then I wired SyndromeValid to some pin at Pmod connector for controlling it on oscilloscope.

Also I enabled Readback CRC in contraint file:

set_property POST_CRC ENABLE
set_property POST_CRC_FREQ 1

But I see nothing on osciloscope ?

Any comments

 

 

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pavel_47
Voyager
Voyager
1,291 Views
Registered: ‎05-30-2018

Resolved !

The constraints were poorly specified:

FRAME_ECC_enableng_constraints_error.JPG

 

Here is the correct usage ([current_design] option was missed):

set_property POST_CRC ENABLE [current_design]
set_property POST_CRC_FREQ 1 [current_design]

Now CRC Readback seems to work ... at least I see activity in LA (FAR changes regularily) and SyndromeValid is visible on oscilloscope.

 

View solution in original post

2 Replies
pavel_47
Voyager
Voyager
1,299 Views
Registered: ‎05-30-2018

In the meantime I modified the setup slightly by adding Logic Analizer and external clock to view other module signals:

module top(
    output SyndromeValid,
    input reset, clk_n, clk_p
    );
    
    wire [25:0] FAR;
    wire [4:0] SynBit;
    wire [12:0] Syndrome;
    wire [6:0] SynWord;
    wire CRC_Error;
    wire ECC_Error;
    wire ECC_ErrorSingle;
    
    wire clk;
    
    ila_0 ila_inst(.clk(clk), .probe0(FAR), .probe1(SynBit), .probe2(Syndrome), .probe3(SynWord),
    				.probe4({CRC_Error, ECC_Error, ECC_ErrorSingle, SyndromeValid}));
    
    clk_wiz_0 clk_wiz_inst(.clk_out1(clk), .reset(reset), .locked(), .clk_in1_p(clk_p), .clk_in1_n(clk_n));
    
    FRAME_ECCE2 #(
          .FARSRC("FAR"),                // Determines if the output of FAR[25:0] configuration register points to
                                          // the FAR or EFAR. Sets configuration option register bit CTL0[7].
          .FRAME_RBT_IN_FILENAME("NONE")  // This file is output by the ICAP_E2 model and it contains Frame Data
                                          // information for the Raw Bitstream (RBT) file. The FRAME_ECCE2 model
                                          // will parse this file, calculate ECC and output any error conditions.
       )
       FRAME_ECCE2_inst (
          .CRCERROR(CRC_Error),             // 1-bit output: Output indicating a CRC error.
          .ECCERROR(ECC_Error),             // 1-bit output: Output indicating an ECC error.
          .ECCERRORSINGLE(ECC_ErrorSingle), // 1-bit output: Output Indicating single-bit Frame ECC error detected.
          .FAR(FAR),                       // 26-bit output: Frame Address Register Value output.
          .SYNBIT(SynBit),                 // 5-bit output: Output bit address of error.
          .SYNDROME(Syndrome),             // 13-bit output: Output location of erroneous bit.
          .SYNDROMEVALID(SyndromeValid),   // 1-bit output: Frame ECC output indicating the SYNDROME output is
                                           // valid.
    
          .SYNWORD(SynWord)                // 7-bit output: Word output in the frame where an ECC error has been
                                           // detected.
    
       );
endmodule

Here is Logic Analyzer output:

ZC706_FRAME_ECC_simulation_in_LA.JPG

As you can see, none signal changes and Frame Address (FAR) is "scotched" to 3BE0000, which is out of the frame adress range for Zynq-7045 device.

Any comments ?

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pavel_47
Voyager
Voyager
1,292 Views
Registered: ‎05-30-2018

Resolved !

The constraints were poorly specified:

FRAME_ECC_enableng_constraints_error.JPG

 

Here is the correct usage ([current_design] option was missed):

set_property POST_CRC ENABLE [current_design]
set_property POST_CRC_FREQ 1 [current_design]

Now CRC Readback seems to work ... at least I see activity in LA (FAR changes regularily) and SyndromeValid is visible on oscilloscope.

 

View solution in original post