cancel
Showing results for 
Show  only  | Search instead for 
Did you mean: 
Highlighted
Visitor
Visitor
320 Views
Registered: ‎07-23-2020

Failed Bitstream Generation: Unspecified I/O Standard Spartan 7

Jump to solution

I have been communicating with several people through other posts recently, and just got my .xdc file to work properly for almost every pin. In the end adding both the Package Pin and IO Standard to the same line using -dict correctly resolved the critical warning: "Set property needs at least one object" 

#set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports CLK]

There are over 200 pins in the project, and all are seemingly working except for the one listed above, which is throwing back an error:

[DRC NSTD-1] Unspecified I/O Standard: 1 out of 100 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: CLK.

Is this saying that I have the pin assigned improperly? Is there a specific location to place the CLK, or does it have to do with something else? 

Also, another pin that I attempted to convert from UCF to XDC had a CLOCK DEDICATED FALSE Tag, but when I tried to implement that, I got a similar issue as above.

set_property -dict {PACKAGE_PIN U1 IOSTANDARD LVCMOS33} [get_ports SSCK]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports SSCK]

Is there a way to include the second portion with everything else, or am I unable to have a CLOCK_DEDICATED_ROUTE FALSE on a port?

0 Kudos
1 Solution

Accepted Solutions
Highlighted
273 Views
Registered: ‎06-21-2017

The 7 Series FPGAs Packaging and Pinout Product Specification UG475 will tell you what you need to know.  Search for MRCC to find the clock capable pins for your package.  Look in the Banking and clocking summary to find the discussion about how many MMCMs are associated with each bank.

View solution in original post

5 Replies
Highlighted
310 Views
Registered: ‎06-21-2017

The line:

#set_property -dict {PACKAGE_PIN U6 IOSTANDARD LVCMOS33} [get_ports CLK]

is a comment.  Is it commented out in your xdc file?  What FPGA/package are you using?

 

As for SSCLK, is it on a clock capable pin?  If so, you do not need the CLOCK_DEDICATED_ROUTE FALSE attribute.  Is SSCLK used as a clock or a signal.  If it is just a signal, you don't need the CLOCK_DEDICATED_ROUTE FALSE attribute.

0 Kudos
Highlighted
Visitor
Visitor
301 Views
Registered: ‎07-23-2020
When I uncomment it, the Implementation fails with the following error:
[Place 30-575] Sub-optimal placement for a clock-capable IO pin and MMCM pair. If this sub optimal condition is acceptable for this design, you may use the CLOCK_DEDICATED_ROUTE constraint in the .xdc file to demote this message to a WARNING. However, the use of this override is highly discouraged. These examples can be used directly in the .xdc file to override this clock rule.
< set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets main_dcm/inst/clk_ext_clk_wiz_v6] >

main_dcm/inst/clkin1_ibufg (IBUF.O) is locked to IOB_X1Y1
main_dcm/inst/mmcm_adv_inst (MMCME2_ADV.CLKIN1) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0

The above error could possibly be related to other connected instances. Following is a list of
all the related clock rules and their respective instances.

Clock Rule: rule_mmcm_bufg
Status: PASS
Rule Description: An MMCM driving a BUFG must be placed on the same half side (top/bottom) of the device
main_dcm/inst/mmcm_adv_inst (MMCME2_ADV.CLKFBOUT) is provisionally placed by clockplacer on MMCME2_ADV_X1Y0
and main_dcm/inst/clkf_buf (BUFG.I) is provisionally placed by clockplacer on BUFGCTRL_X0Y0


0 Kudos
Highlighted
296 Views
Registered: ‎06-21-2017

You may need to move the clock signals around so that they are all on clock capable pins and can reach a MMCM without the CLOCK_DEDICATED_ROUTE FALSE attribute.  Closing timing with this attribute can be very difficult.  Since the schematic is just finished, the board isn't built yet, nothing is set in stone (or copper). 

0 Kudos
Highlighted
Visitor
Visitor
288 Views
Registered: ‎07-23-2020
That helps, thank you. Do you know the resource I can look at to find the right location to place the CLK? In Spartan 6, the IO name has some distinguishing factors that mention clk, but the Spartan 7 FPGA does not have as clear cut naming conventions
0 Kudos
Highlighted
274 Views
Registered: ‎06-21-2017

The 7 Series FPGAs Packaging and Pinout Product Specification UG475 will tell you what you need to know.  Search for MRCC to find the clock capable pins for your package.  Look in the Banking and clocking summary to find the discussion about how many MMCMs are associated with each bank.

View solution in original post