Flash bitstream reprogramming by HDL design in FPGA
I have a question related to in-system FPGA reprogramming. I would like to have ability to reprogram Flash chip containing the bistream of the FPGA by the HDL design in that FPGA and also to reprrogramm the FPGA using the new, uploaded bitstream.
I would like to have layout of SPI Flash memory as follows (rather typical):
Bitstream_v2 (which I can remotly update).
I would like to have a path like: UART - FPGA- HDL_DESIGN - FLASH_REPROGRAMMING of BITSTREAM_V2 section only.
So in general, the FPGA boots using basic firmware, checks if bitstream_V2 is available (for example checks if the first adress is different from 0x0), loads the v2 bistream and restarts. The I can reprogram the flash in section bitstream_v2 using UART interface and for example power cycle the design or restart to have new bistream uploaded.
I'm using the Spartan-3AN chip, that is XC3S50AN. From the various resources I'm not sure, if this approach is possible at all with this chip. The chip flash is connected to the dedicated port in FPGA (not in general purpose lines).
I have read, that maybe the components ICAP could provide a way to select the bistream from the memory and load it. However, could it reprogramm also the Flash memory? I was also thinking about BSCAN component and simple JTAG unit in VHDL taking commands from SVF file generated by Xilinx ISE. I think in newer FPGA the STARTUPE component is providing such functionality?
So the main questions are:
1. If it is possible to reprogram the bitstream of the FPGA flash memory chip by the same FPGA - but it must be Spartan3-AN?