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Angel_fito17
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Registered: ‎03-23-2020

Frequency in Arty-Z7-20

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Hi, I have bought the artyz7-20 board and I have a doubt about the frequency of the board. In the constraints file provided for Digilent the frequency is set to 125 MHz, but in the project of the XADC of Digilent they set the frequency to 100 MHz. Besides in the page of Digilent is posible see the next image where the frequency is 125 MHz. What is the frequency?

arty-z7-clocking.png
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Registered: ‎01-22-2015

@Angel_fito17 

Digilent Inc documentation for the Arty-Z7-20 is pretty clear that the clock entering pin H16 of the Zynq has frequency of 125 MHz.  However, in the Digilent XADCdemo project, the following constraints (as you say) specify the clock period as 10ns (frequency = 100MHz). 

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }]; #set

You will need to ask Digilent Inc about this discrepancy.  

However, if you don’t get an answer from Digilent, then try replacing the above constraints with the following constraints.

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }];  #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock  -period 8.00 -waveform {0 4} [get_ports { clk }];  #set

Then, in the Vivado project, open the xadc_wiz IP and change “DCLK Frequenc(MHz)” to 125MHz.
XADC_Wiz_DCLK.jpg

Good Luck,
Mark

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Registered: ‎01-22-2015

@Angel_fito17 

Digilent Inc documentation for the Arty-Z7-20 is pretty clear that the clock entering pin H16 of the Zynq has frequency of 125 MHz.  However, in the Digilent XADCdemo project, the following constraints (as you say) specify the clock period as 10ns (frequency = 100MHz). 

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }]; #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports { clk }]; #set

You will need to ask Digilent Inc about this discrepancy.  

However, if you don’t get an answer from Digilent, then try replacing the above constraints with the following constraints.

set_property -dict { PACKAGE_PIN H16   IOSTANDARD LVCMOS33 } [get_ports { clk }];  #IO_L13P_T2_MRCC_35 Sch=sysclk
create_clock  -period 8.00 -waveform {0 4} [get_ports { clk }];  #set

Then, in the Vivado project, open the xadc_wiz IP and change “DCLK Frequenc(MHz)” to 125MHz.
XADC_Wiz_DCLK.jpg

Good Luck,
Mark

View solution in original post