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pink12345
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Registered: ‎03-21-2018

Golden and main image generation using multiboot spi

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Hi,

I am trying to use multiboot feature to load 2 fpga bit streams golden image and main image on kintex.

Right now I have all fpga bit stream settings for main image is inside .xdc file and am running synthesize and implementation tcl scripts to generate bit stream.

Following settings are inside xdc file:

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]
set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.GENERAL.COMPRESS True [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property BITSTREAM.CONFIG.SPI_FALL_EDGE Yes [current_design]

set_property BITSTREAM.CONFIG.SPI_32BIT_ADDR Yes [current_design]

 

My question is to generate golden image do i need to run synth and implementation again? or after generating main bit image if I run following commands in my tcl script, it will generate golden image with updated settings.

set_property BITSTREAM.CONFIG.CONFIGFALLBACK ENABLE [current_design]
set_property BITSTREAM.CONFIG.NEXT_CONFIG_ADDR 0xC00000 [current_design]
write_bitstream -force ${build_dir}/${project_name}.runs/impl_1/golden_image.bit
close_design

 

Pl suggest.

Thanks.

 

 

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hj
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Registered: ‎06-05-2013
You can follow any of the 3 methods listed in the AR https://www.xilinx.com/support/answers/58130.html
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
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hj
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Registered: ‎06-05-2013
Please open your golden design routed dcp file(sitting in project/project_runs/impl_x directory) and make the necessary changes to the device properties. And generate the bitstream.
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------
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pink12345
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Registered: ‎03-21-2018

There are many files under routed dcp zipped folder (like dcp.xml, .xdc, _early.xdc, _late.xdc). which one I should open and write settings.

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hj
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Registered: ‎06-05-2013

Follow the steps:

1. Open Vivado

2. File --> Open checkpoint --> Go to impl_1 directory --> look for design_routed.dcp --> open it.

3. Vivado --> Tools --> edit device properties--> make the changes. 

4. write_bitstream update.bit 

(optional Step 5) If you need TCL commands for the above steps. 

5. File --> Project --> Open Journal file --> copy the last few commands for the above steps and add them to your design TCL file. It will do the same after generating the golden bitstream. 

-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
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Don’t forget to reply, kudo, and accept as solution.
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pink12345
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Registered: ‎03-21-2018

Thanks it worked.

However I have one question, instead of opening dcp file, am doing -> open implemented design and then edit bit stream settings and then write_bitstream update.bit.

 Is it okay to do in this way.

 

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hj
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385 Views
Registered: ‎06-05-2013
You can follow any of the 3 methods listed in the AR https://www.xilinx.com/support/answers/58130.html
-------------------------------------------------------------------------------------
For more information please refer to configuration resources https://forums.xilinx.com/t5/FPGA-Configuration/Configuration-Resources/m-p/753763/highlight/true#M5891
-------------------------------------------------------------------------
Don’t forget to reply, kudo, and accept as solution.
-------------------------------------------------------------------------

View solution in original post

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pink12345
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Registered: ‎03-21-2018

Thankyou so much.It worked

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