HTG-830 Won't Boot from BPI without Hardware Manager

[hgraves777]

I am having an issue booting from BPI flash.  I have a simple test design that only turns on a couple LEDS.  After programming the flash, if I cycle power with the JTAG cable connected and the hardware manager running in Vivado, the board will boot.  However if I remove the cable or close the hardware manager, when I apply power the board doesn't boot.

I am using an HTG-830 board with Vivado 2017.3.  If I load the bit file for the example design that came with the board into the BPI, it works as expected (i.e boots up without having to have the hardware manager running).  This leads me to believe that I am missing some setting somewhere.

My method is as follows...
- Synthesize
- Implement
- Generate Bitstream
- Open hardware manager and program the FPGA (works fine)
- Add configuration device
- generate MCS file
 (write_cfgmem -format mcs -interface BPIx16 -size 128 -loadbit  "up 0x0 top.bit" -file top.mcs)
- Program configuration device
- Cycle power (works)
- Remove JTAG cable and cycle power (DOES NOT WORK)
- Reattach JTAG cable and cycle power (works again)

I have added the following lines to my XDC file...

set_property CONFIG_MODE BPI16 [current_design]
set_property BITSTREAM.CONFIG.BPI_SYNC_MODE Type1 [current_design]
set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN Pullnone [current_design]
set_property CFGBVS GND [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]

Any ideas?

[jmcclusk]

Documentation on the HTG-830 is not freely available, so it's hard to investigate..   your Vivado properties look fine, so this might be some sort of hardware issue with the JTAG connections..    Get out the HTG-830 schematic, and pore over it in the JTAG section.   There's got to be a hardware reason why connecting the cable lets the board boot.

[hgraves777]

I thought about that, but the schematic appears to follow the Xilinx App notes for the BPI and JTAG.  Also, the Hitech example file works correctly.  I have asked Hitech, but they have been less than helpful. I was hoping someone else might have had a similar problem.

The problem isn't just that the JTAG cable has to be connected, the hardware manager also needs to be running and connected.  It has to be something simple that I am overlooking.

[jmcclusk]

do you have the source for the Hitech example design?   Can you build it from scratch and get it to work?

[hgraves777 · Accepted solution]

Solved it.

I was the EMCLK property.

set_property BITSTREAM.CONFIG.EXTMASTERCCLK_EN div-1 [current_design]

I am not entirely sure why this was causing a problem since the schematic shows that there is an 80 MHZ clock hooked up to the EMCLK pin.  But removing that line from the XDC file seems to have solved the problem.

[jmcclusk]

Excellent detective work!   That deserves a kudo!