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Contributor
Contributor
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Registered: ‎08-03-2018

Help : How to measure delay time of "Carry4" primitive in a slice ?

Hi

According to "Spartan-6 FPGA Data Sheet: DC and Switching Characteristics" , page 48 , maximume delay from CIN input to COUT output of carry4 in SLICEM is 80ps .(Speed Grade=-3)
I want to implement a delay path with carry4 and i should know the exact delay from CIN to COUT.
How can i measure it in ISE ?
Is there any tool in ISE that can help me to measure delay from CIN to COUT ?
thank you ...
 
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5 Replies
Contributor
Contributor
162 Views
Registered: ‎08-03-2018

Re: Help : How to measure delay time of "Carry4" primitive in a slice ?

Any segestion ... ? 

 

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Scholar drjohnsmith
Scholar
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Registered: ‎07-09-2009

Re: Help : How to measure delay time of "Carry4" primitive in a slice ?

Ah, the old ring osilator on a chip questoin.

  Are you doing encryption or noise generator assignment ?

 

basicaly , as many other shave found on the forum,

   you on to a looser. 

        The time chnages over Process temtratur and Voltage ( PVT )

    the data sheet specifies max times, at the worst corners of PVT,  at other points in the PVT, the time will be less.

 

Ken Chapmans responce on this is IMHO the expert.  He holds several pattents in such things at Xilinx...

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 

<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
107 Views
Registered: ‎08-03-2018

Re: Help : How to measure delay time of "Carry4" primitive in a slice ?


@drjohnsmith wrote:

Ah, the old ring osilator on a chip questoin.

  Are you doing encryption or noise generator assignment ?

 

basicaly , as many other shave found on the forum,

   you on to a looser. 

        The time chnages over Process temtratur and Voltage ( PVT )

    the data sheet specifies max times, at the worst corners of PVT,  at other points in the PVT, the time will be less.

 

Ken Chapmans responce on this is IMHO the expert.  He holds several pattents in such things at Xilinx...

https://forums.xilinx.com/t5/Other-FPGA-Architecture/How-to-implement-a-ring-oscillator-with-routings-of-FPGA-Where/td-p/768444

 


What does this have to do with it?!!

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Scholar drjohnsmith
Scholar
94 Views
Registered: ‎07-09-2009

Re: Help : How to measure delay time of "Carry4" primitive in a slice ?

what does it not answer ?
It shows there is no delay of a carry chain thats fixed , it depends upon placement and routing,

It shows there are other ways of doing what you want to do,
ring oscillators show what can be done with internal delays

Can I just highlight that we do this to help others, we are not paid or rewarded in any way.

If you require other help, please feel free to start a new post,
if you think this does not answer your question, Im sorry I miss understood the work your doing , and the very best to you for the future.
<== If this was helpful, please feel free to give Kudos, and close if it answers your question ==>
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Contributor
Contributor
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Registered: ‎08-03-2018

Re: Help : How to measure delay time of "Carry4" primitive in a slice ?


@drjohnsmith wrote:
what does it not answer ?
It shows there is no delay of a carry chain thats fixed , it depends upon placement and routing,

It shows there are other ways of doing what you want to do,
ring oscillators show what can be done with internal delays

Can I just highlight that we do this to help others, we are not paid or rewarded in any way.

If you require other help, please feel free to start a new post,
if you think this does not answer your question, Im sorry I miss understood the work your doing , and the very best to you for the future.

Hi dear  :)

The path from "CI" to "CO(0)" is fix , is't it ? (i highlighted below...) ... i mean that this path in a slice is somehow "pre_routed". so i think it should have a fix delay.

 

Thank you for your answer...



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