07-11-2020 03:43 AM
i am using spartan 7 fpga,Board frequency is 100MHz but for my application(FIFO) needs 331MHz for writing ,I tried using PLL instantiation and i checked on oscilloscope
i didn't get,can you guide me how to generate.
07-11-2020 10:46 AM
A Spartan 6 PLL should be able to generate 331 MHz. What do you see? How are you routing the signal out of the FPGA? Are you using a DDR register to output the clock as is recommended? What is the Select IO type? Are you going through a connector or are you looking on the board? What is the bandwidth of you scope and scope probes?
07-12-2020 10:17 PM
07-13-2020 03:19 AM
You should use an ODDR register to drive a clock out of the FPGA. Look in the Select IO Users guide (UG471) for a discussion. What about the other questions? What are the bandwidth of your scope and probes? Are you probing on your board or at a connector? Is the signal terminated in any way?
07-13-2020 06:49 AM - edited 07-13-2020 06:50 AM
What kind of connector Is it a PMOD or an FMC connector? PMODs are poor choices for high frequency signals. Why do you expect to see a 330 MHz signal on a scope with only a 60MHz bandwidth?
07-13-2020 06:59 AM
As @bruce_karaffa indicates, you need:
1 - To have that output with a proper output buffer
2 - To have bring the signal to a high speed connector (FMC, SMA, etc)
2 - A proper oscilloscope with at least 1 Gsps, 500 MHz bandwidth
Another approach would be to take your 300 MHz signal inside the FPGA, divide it by something appropriate using some HDL) to have a few MHz and have that signal/ clock out to any pin (a PMOD would work with up to 5 MHz)