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Visitor igor@arineta
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Registered: ‎12-14-2014

How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Dear All,

 

Please advise how to calculate a time that takes a master configuration of 7-Series FPGA with Asynchronous BPI flash memory.

 

 

Thanks in advance...

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Registered: ‎01-22-2015

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Using Fig. 5.4 in UG470, the time to configure the 7-Series FPGA in master BPI mode is roughly calculated as T(POR)+T(LOAD), where T(POR) < 50ms is given by Table 71 in DS182 and T(LOAD) is the time it takes to clock-in the configuration file from the BPI flash.

 

To calculate T(LOAD) you need the size of the configuration file (from Table 1-1 in UG470), the read-access time of the flash, and the data-width of the flash. For example, the Kintex-7 (7K160T) has a configuration file size of ~54Mb and the Micron MT28GU BPI flash has 16-bit data width and 96ns read-access time.  So, the calculation for T(LOAD) is:

                                                    54Mb * 96ns / 16b = 324ms

Adding T(POR)=50ms gives a total configuration time of ~374ms.  This is far from meeting the 100ms boot time requirement for PCI Express (PCIe).  For more information about meeting the PCIe 100ms boot time requirement see XAPP1179.

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Registered: ‎01-22-2015

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Using Fig. 5.4 in UG470, the time to configure the 7-Series FPGA in master BPI mode is roughly calculated as T(POR)+T(LOAD), where T(POR) < 50ms is given by Table 71 in DS182 and T(LOAD) is the time it takes to clock-in the configuration file from the BPI flash.

 

To calculate T(LOAD) you need the size of the configuration file (from Table 1-1 in UG470), the read-access time of the flash, and the data-width of the flash. For example, the Kintex-7 (7K160T) has a configuration file size of ~54Mb and the Micron MT28GU BPI flash has 16-bit data width and 96ns read-access time.  So, the calculation for T(LOAD) is:

                                                    54Mb * 96ns / 16b = 324ms

Adding T(POR)=50ms gives a total configuration time of ~374ms.  This is far from meeting the 100ms boot time requirement for PCI Express (PCIe).  For more information about meeting the PCIe 100ms boot time requirement see XAPP1179.

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Observer nate.wang
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Registered: ‎03-04-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Hi Sir,

 

I have the same question.

 

Currently I am using BPI flash(Micron 28f512p33) and this device supports synchronous read mode.

I set CCLK to 50MHz, and from below table we know the bit stream size of XC7K325T is 91,548,896 bits, 

 

未命名.png

 

so configuration time is about 91,548,894 bit / 50MHz / 16bit = 114ms, which meets my measurement as below, as you can see I still have ~140ms buffer time before PCI-E reset signal.

 

measure.png

 

However, since Micron is going to phase out their BPI flash, I am considering to change to Cypress/Spansion S29GL512S (http://www.cypress.com/part/s29gl512s11dhiv23), and this device does not have a clock input pin, meaning that only asynchronous read mode is supported.

So the question is, if I change to S29GL512S, in asynchronous read mode, how much time is required to configure FPGA ? Is there a theoretical way to calculate this time period ?

 

Another question, for now I am still using Micron 28f512p33 on board, may I set the configuration file(*.bit/*.mcs) to asynchronous mode to simulate the condition of using S29GL512S ? I cannot find the relative setting in "bitstream settings" of Vivado.

 

By the way, in reply to markg's response, from data sheet 96ns is the initial read access time, not the time during synchronous read, in below figure it shows 108/133MHz synchronous burst read is supported by MT28GU, are you sure T(LOAD) is as long as 54Mb * 96ns / 16b = 324ms ?

 micron.png

 

 

Appreciate for your kindly help !

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Registered: ‎01-22-2015

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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By the way, in reply to markg's response, from data sheet 96ns is the initial read access time, not the time during synchronous read

 

Pages 66-68 of the MT28GU datasheet have Asynchronous Specifications that say “READ cycle time” is 96ns min. However, the comment “- 96ns initial read access” on page 1 has caused me some doubt – especially the word “initial”, which I can’t find elsewhere in the datasheet.  I suggest you contact Micron to clarify.

 

I am sorry that I cannot help answer your other very good questions.

Mark

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Observer nate.wang
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Registered: ‎03-04-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Thanks Mark.

 

This question is really critical to me, is there any other expert here to help me and igor ? Thanks !

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Registered: ‎06-05-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Check the following XAPP (Page#10-11) https://www.xilinx.com/support/documentation/application_notes/xapp587-bpi-fast-configuration.pdf

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Observer nate.wang
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Registered: ‎03-04-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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thanks harshit.

 

according to below description, in asynchronous mode maximum CCLK frequency is determined by T_BPICCO + T_BPIDCC + T_ACC, and since T_ACC(refer to datasheet of the flash chip) is at the range of about 100ns, CCLK frequency in asynchronous mode is much lower than in synchronous mode(max 66MHz when using internal CCLK). so configuration time is much higher in asynchronous mode.

未命名.png

 

one more question, does "Type 1" in below figure refers to synchronous mode ? May I just set it to "Type 2" to simulate asynchronous mode configuration even when the flash chip on my board support synchronous mode configuration ? Thanks again !

 

未命名2.png

 

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Observer nate.wang
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Registered: ‎03-04-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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By the way, just want to confirm that using Tandem configuration for PCIe(XAPP1179) is the only choice for Xilinx users if implementing a PCIe device on Xilinx FPGA ? To be honest, I cannot understand "Enabling Tandem Configuration in the Kintex-7 Connectivity TRD" section of XAPP1179, it would be good if there is any other simpler way to overcome this problem, thanks.

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Xilinx Employee
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Registered: ‎11-17-2008

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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@nate.wang,

 

Is Tandem Configuration the only way?  No, of course not, but it depends on your needs.  Not all devices will plug into an open PCIe system and therefore require 100ms enumeration -- just use a standard PCIe IP for this.  Power supply staging, holding reset, or other techniques can be used to give the FPGA a head start so it can completely configure before the enumeration process starts. Ask yourself if 100ms is truly a requirement.

 

If you need strict adherence to the standard, then you need to either push the bitstream in more quickly, or reduce the size of the bitstream.  The former can be done with BPI (for now) or external schemes to take advantage of the SelectMAP bandwidth.  The latter can be done with bitstream compression -- this is much more effective when combined with PR, removing a big chunk of the initial logic -- or Tandem Configuration.  All these options have tradeoffs, so I would suggest prioritizing your needs and looking at details of each.  You can find more on Tandem in the PCIe IP guide, PG054 or PG023, depending on your 7 series target.

 

thanks,

david.

Observer nate.wang
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Registered: ‎03-04-2013

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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thanks Davidd.

 

Not all devices will plug into an open PCIe system and therefore require 100ms enumeration

>> unfortunately my product is a PCI-e card needs to be plugged onto PC motherboards on the market

 

The latter can be done with bitstream compression -- this is much more effective when combined with PR, removing a big chunk of the initial logic

>> I tried bitstream compression and the size of *.bit/*.mcs file is truly compressed by about 20%, so this is a plus but not a solution. Could you explain more on "combined with PR, removing a big chunk of the initial logic" ?

未命名.png

 

or Tandem Configuration

>> unfortunately again I am not using the PCI-e IP from Xilinx, instead I use the IP from PLDA which makes me more difficult to do Tandem configuration

 

thanks again !

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Xilinx Employee
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Registered: ‎11-17-2008

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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@nate.wang,

 

Okay, if you're using a non-Xilinx PCIe IP and you must plug into general motherboards (e.g. you don't have control over power or reset), you're left with two options as I see it:  brute force or PR. 

 

Brute force again means that you build some sort of external configuration scheme that maximizes bandwidth so that you can push the full bitstream in fast enough.  There are some different schemes that could work there, but you'll need to look around and do some math to see if that could be an option.  Hardware footprints, cost, and complexity are all considerations here, but the FPGA design would not have to change.

 

PR means that you put as much of the design as you can into a Reconfigurable Partition, then when you generate your boot bitstream, you replace it with a black box first so that bitstream compression can be very effective.  Will you be able to meet your goals with this approach?  That's something I can't answer, as there are a few factors:

1. How big is the PLDA core?  I'm guessing it's not that small.

2. With 7 series FPGAs, IO, clocks and GTs must remain in static, which means they'll be in that primary boot bitstream.

3. How effective is compression?  That varies per design, and while I've seen upwards of 80-90%, in this case (PLDA core in a 7K325T) I think it won't be that high, maybe 60-70%.  Might not be enough.

4. Can you fit the design and close timing?  7 series PR is solid, but not as efficient as UltraScale.  If your design is full/challenging now, adding PR will not be trivial.

5. And finally, if all of that can get the static design in quickly enough, you still need to load in the remainder of the design.  That is part of your overall design, whether you build an ICAP loader or push through an external port.

 

Before we developed Tandem Configuration in Vivado, we used this compressed PR approach in ISE for Virtex-6.  Read about this in XAPP883: https://www.xilinx.com/support/documentation/application_notes/xapp883_Fast_Config_PCIe.pdf.

 

So it comes down to where this challenge is solved, internal or external to the FPGA.

 

thanks,

david.

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Registered: ‎01-22-2015

Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Nate,

 

Have you considered the slave-SelectMAP method mentioned by davidd?  The associated hardware and connections are shown on page 42 of UG470. This method uses a microprocessor (instead of flash memory) to store the configuration file and to pass the configuration file to the FPGA at power-up.  I see big advantages to this method:

  1. The microprocessor controls the configuration clock, EMCCLK, and you have gotten rid of the extremely variable CCLK.   The EMCCLK will probably be faster than the 50MHz CCLK you were using (see page 10 of XAPP587 for calculation of EMCCLK max speed).
  2. There is no flash memory part. That is, you no longer need worry about flash memory parts that are discontinued or in short supply.
  3. The data bus for slave-SelectMAP can be up to 32-bits wide!

In your 12Jul18 post, you calculated configuration time with the discontinued BPI synchronous flash as follows:

       91,548,894 bit / 50MHz / 16bit = 114ms

 

However, with 32-bit wide slave-SelectMAP, I think the calculation might be:

       91,548,894 bit / 50MHz / 32bit = 57ms!

 

Finally, a reminder that smaller FPGAs have smaller-size configuration files.  So, if you can use a smaller FPGA then you should be able to configure it faster at power-up.

 

Mark

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Observer nate.wang
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Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Hi David and Mark,

 

Thanks for the reply, now I am clear all the possible choices, though there is no simple choice in my case ...

 

Hi Mark,

 

simple question, in slave-SelectMAP method, what does the "configuration memory source" mean ? If it still refers to a NOR flash, I still have the same problem comparing to BPI/SPI configuration mode, thanks.

未命名.png

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Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Refer this following XAPP https://www.xilinx.com/support/documentation/application_notes/xapp502.pdf

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Re: How to Calculate a Time of 7-Series FPGA Master Configuration with Asynchronous BPI Flash Memory

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Hi Nate,

 

   …in slave-SelectMAP method, what does the "configuration memory source" mean ?

It seems to me that you are asking all the right questions. I am sorry that I don’t have the experience to expertly guide you.

 

The XAPP502 reference suggested by harshit and the newer XAPP583 indicate that the “configuration memory source" is usually a flash memory part.  As you imply, this does not seem to have gotten us anywhere since we must still deal with bandwidth limitations of the flash part.  However, the microcontroller has the flexibility to increase bandwidth in different ways (eg. by simultaneously reading from multiple flash parts in parallel).

 

In some applications, the microcontroller may have sufficient program memory for the FPGA configuration file to be hard-coded along with the microcontroller firmware.  For example, I see that some of the microchip.com 32-bit microcontrollers <here> have 2048KB~16Mb of program memory. This is not enough to hold your 96Mb FPGA configuration file, but it might be enough to hold the configuration file for smaller FPGAs.

 

Mark

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