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Visitor
Visitor
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Registered: ‎11-25-2019

How to configure Instruction into TMR BRAM?

I am using Nexys Video board with Artix-7 FPGA. We have a custom IP designed that scrubs a TMR BRAM memory.

I want to know how to replicate my program or .elf file into the 3 BRAMs such that they have the same content at load time?

Earlier there was data2mem as one of the solutions, but that seems to have been discontinued. Is there something that I can use now which is simpler hopefully?

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Xilinx Employee
Xilinx Employee
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Registered: ‎03-07-2018

Hi @dev2293 

UpdateMEM in Vivado is the equivalent to Data2MEM in ISE.

Check UG898-vivado-embedded-design (Chapter 7) for more details.

You can always check UG911-vivado-migration guide for ISE to Vivado design migration.

Regards,
Bhushan

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