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Observer
Observer
562 Views
Registered: ‎06-15-2018

How to delete a Design internally

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Hi All,

I'm designing a secure system with verilog. Can I delete My design files (bitstream files from FPGA board) internally with verilog? If possible how it could be done? Any information is appreciated.

Thanks in advance.

 

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Xilinx Employee
Xilinx Employee
517 Views
Registered: ‎06-21-2018

Hi vmerter,

Are the bit files on a Flash PROM (such as SPI or BPI) or only on the FPGA?

When you power down an FPGA, it loses its configuration. If you want to erase a Flash PROM, that can be done, too.

Thanks,
Andres

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Moderator
Moderator
523 Views
Registered: ‎05-02-2017

 

hi @vmerter,

 

I believe and assume you wanted to deleted or format  the bitstream(.bit file ) through the Verilog code  which is inside the FPGA once it is configured unfortunately  this is cannot be done.

 

if I have answered your query , please close this forum by accepting the solution. if not please let me know your inputs

 

Chandra  

 

Regards
Chandra sekhar
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Xilinx Employee
Xilinx Employee
518 Views
Registered: ‎06-21-2018

Hi vmerter,

Are the bit files on a Flash PROM (such as SPI or BPI) or only on the FPGA?

When you power down an FPGA, it loses its configuration. If you want to erase a Flash PROM, that can be done, too.

Thanks,
Andres

View solution in original post